m395t5160dz4-cd56/e66 Samsung Semiconductor, Inc., m395t5160dz4-cd56/e66 Datasheet - Page 23

• Manufacturer Part Number: m395t5160dz4-cd56/e66
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

Table 14 : Differential Receiver Input Specifications
Notes :
1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the
2. Single-ended voltages below that value that are simultaneously detected on D+ and D-are interpreted as the Electrical Idle condition.
3. Multiple lanes need to detect the El condition before the device can act upon the El detection.
4. Specified at the package pins into a timing and voltage compliance test setup.
5. The single-pulse mask provides suffcient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse
6. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the RX. Each symbol must
7. This number does not include the effects of SSC or reference clock jitter.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
10. Allows for 15 mV DC offset between transmit and receive devices.
FBDIMM
Differential peak-to-peak input voltage for large volt-
age swing
Maximum single-ended voltage in El condition
Maximum single-ended voltage in Ei condition (DC
only)
Maximum peak-to-peak differential voltage in El
condition
Single-ended voltage (w.r.t. V
Single-pulse peak differential input voltage
Amplitude ratio between adjacent symbols
Maximum RX inherent timing error, 3.2 and 4.0 Gb/
x
Maximum RX inherent deterministic timing eror, 3.2
and 4.8 Gb/s
Single-pulse width as zero-voltage crossing
Single-pulse width at minimum-level crossing
Differential RX input rise/fall time
Common mode fo the input voltage
Differential RX output rise/fall time
Common mode of input voltage
AC peak-to-peak common mode of input voltage
Ratio of V
Differential return loss
Common mode return loss
RX termination impedance
D+/D- RX Impedance difference
Lane-to lane PCB skew at RX
Minimum RX drift tolerance
Minim data tracking 3dB bandwidth
Electrical idle entry detect time
Electrical idle exit detect time
Bit Error Ratio
Worst-case margins are determined for the case with transmitter using small voltage swing.
pin.
comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols.
mask and the cumulative eyemask.
RX-CM-ACp-p
Parameter
to minimum V
SS
) on D+/D-
RX-DIFFp-p
V
T
T
V
V
RX-DIFF-ADJ-RATIO
T
V
RX-RISE
V
EI-ENTRY-DETECT
RX-CM-EH-RATOP
R
L
T
V
V
RX-IDLE-DIFFp-p
EI-EXIT-DETECT
RX-DIFF-PULSE
V
RX-IDLE-SE-DC
V
RX-PCB-SKEW
T
RX-MATCH-DC
RX-TJ-MAX4.8
T
T
V
RX-DJ-DD-4.8
RX-CM-ACp-p
RL
T
RX-IDLE-SE
RL
RX-DIFFp-p
RX-TJ-MAX
Symbol
RX-PW-ZC
RX-PW-ML
V
V
RX-DJ-DD
RX-DRIFT
F
BER
RX-CM
RX-DIFF
R
RX-SE
RX-CM
TRK
RX
T
RX-FALL
23 of 31
-300
0.55
MIN
170
120
400
0.2
0.2
85
50
41
9
6
Values
10
MAX
TBD
TBD
TBD
TBD
900
400
270
0.4
0.3
75
50
65
45
55
60
30
4
6
-12
Units
MHz
mV
mV
mV
mV
mV
mV
mV
mV
dB
dB
UI
UI
UI
UI
UI
UI
ps
UI
ps
ns
ns
%
%
Ω
Lane-to-lane skew at the receiver that
must be tolerated. Note 14
Rev. 1.01 March 2008
1GHz-2.4 GHz, Note 12
1GHz-2.4 GHz, Note 12
DDR2 SDRAM
20~80% voltage
EQ 6, Note1, 10
EQ 7, Note 1
EQ 5, Note1
Comments
4,7,8,9
4,7,8,9
4,7,8
4,7,8
EQ 8
2,3
2,3
4,5
4,6
4,5
4.5
11
13
15
16
17
18
3
4