m395t5160dz4-cd56/e66 Samsung Semiconductor, Inc., m395t5160dz4-cd56/e66 Datasheet - Page 24

• Manufacturer Part Number: m395t5160dz4-cd56/e66
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

FBDIMM
11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode spec-
12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully de-
13. The termination small signal resistance; tolerance across voltage from 100 mV to 400 mV shall not exceed +/-5 W with regard to
14. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the
15. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and
16. This bandwidth number assume the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05 UI,
17. The specified time includes the time required to forward the El entry condition.
18. BER per differential lane.
V
(V
V
R
RX-DIFFp-p
RX-CM-AC
RX-MATCH-DC
RX-CM
ification. For example, if V
mV)and V
signed.
the average of the values measured at 100 mV and at 400 mV for that pin.
component of the end-to-end channel skew in the AMB specification.
temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver.
= DC(avg) of [V
=((Max[V
= 2x[V
RX-CM-AC-p-p
= 2x((R
RX-D
RX-D+
RX-D+
+-V
RX-D+
.
+ V
RX-D-
-R
RX-D
RX-DIFFp-p
RX-D-
+ V
] (EQ5)
)/2)((Min [V
RX-D-
)/(R
] /2) (EQ 6)
RX-D+
is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV*0.45=90
RX-D+
+ R
RX-D-
+ V
) (EQ 8)
RX-D-
)/2) (EQ 7)
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Rev. 1.01 March 2008
DDR2 SDRAM