m395t5160dz4-cd56/e66 Samsung Semiconductor, Inc., m395t5160dz4-cd56/e66 Datasheet - Page 8

• Manufacturer Part Number: m395t5160dz4-cd56/e66
• Description: Ddr2 Fully Buffered Dimm
• Manufacturer: Samsung Semiconductor, Inc.

Note : The values in “ X” fields in non-reserved commands above may be driven onto the DRAM device pins.
2.5 Southbound Command Delivery
A DRAM command located in the "A" command may be delivered to the DRAM devices as soon as the 14-bit (10-bits in fail-over) CRC
is checked. This minimizes DRAM access latency by allowing the command to be delivered after the first 4 transfers of the frame have
been received. The "A" command is transferred immediately to the DRAM pins with minimum delay whereas the "B" and "C" command
are delivered one DRAM clock later. To minimize memory access latency the read related Activate, Read (if the page is open) and
explicit Precharge commands to a rank of DRAM devices should be placed in the "A" command, if possible. Figure 6 illustrates the deliv-
ery of the three potential commands in a frame to three separate DRAM channels.
Command "A" is delivered in this case to the DRAM devices on DIMM 3 as soon as the command can traverse the AMB buffer. The "B"
and "C" commands are delayed and presented to two other DRAM channels on the following clock. See below figure7~10 for Basic
Read & Write Operations
Northbound consists of 14 differential signal pairs (lane), physically 28 signaling line. Southbound Format has 14x12 (14 IO (or Lane) x
12 IO switching) frame format, which deliver 14x12 bit information per one DRAM clock. One north bound frame is divided into two. Both
frame deliver read data from DRAM
Activate
Write
Read
Precharge All
Precharge Single
Auto (CBR) Refresh
Enter Self Refresh
Exit Self Refresh/
Exit Power Down
Enter Power Down
reserved
FBDIMM
Figure 6 : FBDIMM Command Delivery Rules
Figure 5 : FBDIMM Command Encoding & SB Frame
DRAM Cmnds
FBD southbound
FBD northbound
Southbound Command Frame Format*
DIMM 1 cmd
DIMM 2 cmd
DIMM 3 cmd
DIMM 4 cmd
Note :
1. aE[0~12] : CRC Checksum of the A Command
2. F[0~1] : Frame Type
3. FE[0~21] : CRC Checksum of 72bit data
4. CRC : Cyclic Redundancy Check
Bit
10 FE15
11 FE14
0
1
2
3
4
5
6
7
8
9
cmd/data
cmd/data
FE21
FE20
FE19
FE18
FE17
FE16
aE0 aE7 aE8 F0=0 aC20 aC16 aC12 aC8 aC4 aC0
aE1 aE6 aE9 F1=0 aC21 aC17 aC13 aC9 aC5 aC1
aE2 aE5 aE10 aE13 aC22 aC18 aC14 aC10 aC6 aC2
aE3 aE4 aE11 aE12 aC23 aC19 aC15 aC11 aC7 aC3
FE0 FE7 FE11
FE1 FE6 FE10
FE2 FE5 FE9 FE13
FE3 FE4 FE8 FE12
9
8
0
0
0
0
0
0
0
0
“A”
“B”
“C”
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
DS2 DS1 DS0
7
0
0
0
0
0
0
0
0
23
1
X
6
0
0
0
0
0
0
0
0
22
X
“A”
2
bC20 bC16 bC12 bC8 bC4 bC0
bC21 bC17 bC13 bC9 bC5 bC1
bC22 bC18 bC14 bC10 bC6 bC2
bC23 bC19 bC15 bC11 bC7 bC3
cC20 cC16 cC12 cC8 cC4 cC0
cC21 cC17 cC13 cC9 cC5 cC1
cC22 cC18 cC14 cC10 cC6 cC2
cC23 cC19 cC15 cC11 cC7 cC3
21
5
X
“C”
“B”
20
4
1
0
0
0
0
0
0
0
0
0
3
DRAM Addr
19
3
1
1
0
0
0
0
0
0
0
4
18
2
1
0
1
1
1
1
1
1
1
RS
RS
RS
RS
RS
RS
RS
RS
RS
17
X
1
5
16
X
X
X
X
X
X
0
8 of 31
DRAM Bank
15
X
X
X
X
X
X
A CMD
B CMD
C CMD
14
X
X
X
X
X
X
1. CMD A transferred immediately
2. CMD A, B, C cannot target the same DIMM
3. Host is responsible for scheduling CMD
13
X
X
X
X
X
X
12
1
1
1
1
0
0
0
11
1
1
0
0
1
1
0
CLK_REF
CLK_DRAM
Packet T/F
10
X
1
0
1
0
1
0
DRAM Bank & Address
DRAM Bank & Address
DRAM Bank & Address
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
X
X
X
X
X
X
X
7
6
X
X
X
X
X
X
X
Rev. 1.01 March 2008
12 transfers
DDR2 SDRAM
X
X
X
X
X
X
X
5
4
X
X
X
X
X
X
X
3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
x10 bits
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0