mt9v032 aptina, mt9v032 Datasheet - Page 13

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Output Data Timing
Figure 7:
Figure 8:
Table 4:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Parameter
A
P1
P2
Q
Frame Time
Timing Example of Pixel Data
Row Timing and FRAME_VALID/LINE_VALID Signals
LINE_VALID
D
OUT
PIXCLK
Name
Active data time
Frame start blanking
Frame end blanking
Horizontal blanking
(9:0)
The data output of the MT9V032 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows
PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled,
the PIXCLK is HIGH for one complete master clock master period and then LOW for one
complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for
two complete master clock periods and then LOW for two complete master clock
periods. It is continuously enabled, even during the blanking period. Setting R0x74
bit[4] = 1 causes the MT9V032 to invert the polarity of the PIXCLK.
The parameters P1, A, Q, and P2 in Figure 8 are defined in Table 4.
Number of master clocks
FRAME_VALID
Blanking
LINE_VALID
(9:0)
P 0
(9:0)
P1
P 1
Equation
R0x04
R0x05 - 23
23 (fixed)
R0x05
A
14
(9:0)
Valid Image Data
P2
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Q
(9:0)
P 3
...
...
...
(9:0)
A
P 4
Aptina reserves the right to change products or specifications without notice.
Q
...
...
...
...
Default Timing at 26.66 MHz
752 pixel clocks
= 752 master
= 28.20μs
71 pixel clocks
= 71master
= 2.66μs
23 pixel clocks
= 23 master
= 0.86μs
94 pixel clocks
= 94 master
= 3.52μs
©2005 Aptina Imaging Corporation. All rights reserved.
A
P n-1
(9:0)
Output Data Format
P2
(9:0)
P n
Blanking