mt9v032 aptina, mt9v032 Datasheet - Page 26

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 8:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Bit
0x0A (10) Shutter Width Control
0x0B (11) Total Shutter Width
0x0C (12) Reset
0x0D (13) Read Mode
14:0
3:0
7:4
1:0
8
9
0
1
T2 Ratio
T3 Ratio
Exposure Knee
Point Auto Adjust
Enable
Single Knee
Enable
Total Shutter
Width
Soft Reset
Auto Block Soft
Reset
Row Bin
Bit Name
Register Descriptions (continued)
One-half to the power of this value indicates the ratio of
duration time t
adjusted to level V2 to total integration when exposure
knee point auto adjust control bit is enabled. This
register is not shadowed, but any change made does
not take effect until the following new frame.
t
One-half to the power of this value indicates the ratio of
duration time t
adjusted to level V3 to total integration when exposure
knee point auto adjust control bit is enabled. This
register is not shadowed, but any change made does
not take effect until the following new frame.
t
Note: t
0 = Auto adjust disabled.
1 = Auto adjust enabled.
0 = Single knee disabled.
1 = Single knee enabled.
Total integration time in number of rows. This value is
used only when AEC is disabled only (bit 0 of Register
175). This register is not shadowed, but any change
made does not take effect until the following new
frame.
Setting this bit causes the sensor to abandon the
current frame by resetting all digital logic except two-
wire serial interface configuration. This is a self-
resetting register bit and should always read “0.” (This
bit de-asserts internal active LOW reset signal for 15
clock cycles.)
Setting this bit causes the sensor to reset the automatic
gain and exposure control logic. This is a self-resetting
register bit and should always read “0.” (This bit de-
asserts internal active LOW reset signal for 15 clock
cycles.)
0 = Normal operation.
1 = Row bin 2. Two pixel rows are read per row output.
Image size is effectively reduced by a factor of 2
vertically while data rate and pixel clock are not
affected. Resulting frame rate is increased by 2.
2 = Row bin 4. Four pixel rows are read per row output.
Image size is effectively reduced by a factor of 4
vertically while data rate and pixel clock are not
affected. Resulting frame rate is increased by 4.
3 = Not valid.
2
3
= Total integration × (½)
= Total integration × (½)
1
= Total integration - t
2
3
, when saturation control gate is
, when saturation control gate is
Bit Description
t2_ratio
t3_ratio
2
-
.
.
t
3
.
27
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Default in
Hex (Dec)
(480)
1E0
4
6
1
0
0
0
0
Aptina reserves the right to change products or specifications without notice.
Shadowed
N
N
N
N
N
N
Y
Y
©2005 Aptina Imaging Corporation. All rights reserved.
1–32767
Values
0, 1, 2
Legal
(Dec)
0–15
0–15
0, 1
0, 1
0,1
0,1
Registers
Read/
Write
W
W
W
W
W
W
W
W