mt9v032 aptina, mt9v032 Datasheet - Page 34

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 8:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Bit
0xB3 (179) LVDS Data Control
0xB4 (180) LVDS Latency
0xB5 (181) LVDS Internal Sync
0xB6 (182) LVDS Payload Control
0xB7 (183) Stereoscopy Error Control
0xB8 (184) Stereoscopy Error Flag
0xB9 (185) LVDS Data Output
0xBA (186) AGC Gain Output
0xBB (187) AEC Exposure Output
0xBC (188) AGC/AEC Current Bin
15:0
15:0
2:0
1:0
6:0
5:0
4
0
0
0
1
2
0
Data Delay
Element Select
LVDS Driver
Power-down
Stream Latency
Select
LVDS Internal
Sync Enable
Use 10-bit Pixel
Enable
Enable Stereo
Error Detect
Enable Stick
Stereo Error Flag
Clear Stereo Error
Flag
Stereoscopy Error
Flag
Combo Reg
AGC Gain
AEC Exposure
Current Bin
Bit Name
Register Descriptions (continued)
The amount of data delay that minimizes inter-sensor
skew.
When set, data LVDS driver is disabled.
The amount of delay so that the two streams are in
sync.
When set, the MT9V032 generates sync pattern (data
with all zeros except start bit) on
LVDS_SER_DATA_OUT.
When set, all 10 pixel data bits are output in stand-
alone mode. Control signals are embedded. If clear, 8
bits of pixel data are output with 2 control bits. See
“LVDS Output Format” on page 58 for additional
information.
Set this bit to enable stereo error detect mechanism.
When set, the stereo error flag remains asserted once
an error is detected unless clear stereo error flag (bit 2)
is set.
Set this bit to clear the stereoscopy error flag (R0xB8
returns to logic 0).
Stereoscopy error status flag. It is also directly
connected to the ERROR output pin.
This 16-bit value contains both 8-bit pixel values from
both stereoscopic master and slave sensors. It can be
used in diagnosis to determine how well in sync the two
sensors are. Captures the state when master sensor has
issued a reserved byte and slave has not.
Note: This register should be read from the stereoscopic
master sensor only.
Status register to report the current gain value obtained
from the AGC algorithm.
Status register to report the current exposure value
obtained from the AEC Algorithm.
Status register to report the current bin of the
histogram.
Bit Description
35
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Default in
Hex (Dec)
00C8
(200)
(16)
10
0
1
0
0
0
0
0
0
Aptina reserves the right to change products or specifications without notice.
Shadowed
Y
Y
Y
Y
Y
Y
Y
Y
©2005 Aptina Imaging Corporation. All rights reserved.
Values
Legal
(Dec)
0–7
0–3
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
Registers
Read/
Write
W
W
W
W
W
W
W
W
R
R
R
R
R