mt9v032 aptina, mt9v032 Datasheet - Page 69

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Configuration of Sensor for Stereoscopic Serial Output with Internal PLL
Figure 47:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
BYPASS_CLKIN
SER_DATAIN
LVDS
LVDS
1. PLL in non-bypass mode
2. PLL in x 18 mode (stereoscopy)
Stereoscopic Topology
X 1 8/X 1 2 PL L
SENSOR
SENSOR
SLAVE
SER_DATAOUT
10. Individual WRITE to slave sensor, setting it as a stereo slave (set R0x07[6] = 1).
11. Individual WRITEs to master sensor to minimize the inter-sensor skew (set
12. Broadcast WRITE to issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0).
1. Power up the sensors.
2. Broadcast WRITE to de-assert LVDS power-down (set R0xB1[1] = 0).
3. Individual WRITE to master sensor putting its internal PLL into bypass mode (set
4. Broadcast WRITE to both sensors to set the stereoscopy bit (set R0x07[5] = 1).
5. Make sure all resolution, vertical blanking, horizontal blanking, window size, and
6. Broadcast WRITE to enable LVDS driver (set R0xB3[4] = 0).
7. Broadcast WRITE to enable LVDS receiver (set R0xB2[4] = 0).
8. Individual WRITE to master sensor, putting its internal PLL into bypass mode (set
9. Individual WRITE to slave sensor, enabling its internal PLL (set R0xB1[0] = 0).
In this configuration the internal PLL generates the shift-clk (x18) in phase with the
system-clock. The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be
connected to a deserializer (clocked at approximately the same system clock frequency).
Figure 47 shows how a standard off-the-shelf deserializer can be used to retrieve back
D
out LINE_VALID and FRAME_VALID embedded within the pixel data stream.
Typical configuration of the master and slave sensors:
OUT
R0xB1[0] = 1).
AEC/AGC configurations are done through broadcast WRITE to maintain lockstep.
R0xB1[0] = 1).
R0xB2[2:0], R0xB3[2:0], and R0xB4[1:0] appropriately). Use R0xB7 and R0xB8 to get
lockstep feedback from stereo_error_flag.
LVDS
(9:2) for both the master and slave sensors. Additional logic is required to extract
SHIFT_CLKOUT
LVDS
1. PLL in bypass mode
BYPASS_CLKIN
SER_DATAIN
LVDS
LVDS
MASTER
70
SENSOR
LV and FV are embedded in the data stream
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
SER_DATAOUT
SLAVE
FROM
PIXEL
8
LVDS
DS92LV16
LVDS
SHIFT_CLKOUT
MASTER
PIXEL
FROM
8
Appendix A – Serial Configurations
Aptina reserves the right to change products or specifications without notice.
26.6 MHz
26.6 MHz
Osc.
Osc.
©2005 Aptina Imaging Corporation. All rights reserved.
5 meters (maximum)