mt9v032 aptina, mt9v032 Datasheet - Page 55

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mt9v032

Manufacturer Part Number
mt9v032
Description
1/3-inch Wide-vga Cmos Digital Image Sensor
Manufacturer
aptina
Datasheet

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Interlaced Readout
Figure 32:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Spatial Illustration of Interlaced Image Readout
The MT9V032 has two interlaced readout options. By setting R0x07[2:0] = 1, all the even-
numbered rows are read out first, followed by a number of programmable field blanking
(R0xBF, bits 7:0), and then the odd-numbered rows and finally vertical blanking
(minimum is 4 blanking rows). By setting R0x07[2:0] = 2, only one field is read out;
consequently, the number of rows read out is half what is set in R0x03. The row start
address (R0x02) determines which field gets read out; if the row start address is even, the
even field is read out; if row start address is odd, the odd field is read out.
When interlaced mode is enabled, the total number of blanking rows are determined by
both field blanking register (R0xBF) and vertical blanking register (R0x06). The follow-
ings are their equations.
Similar to progressive scan, FRAME_VALID is logic LOW during the valid image row only.
Binning should not be used in conjunction with interlaced mode.
Vertical Blanking = R0x06, bits 8:0 -R0xBF, bits 7:0
P
with
P
m-2,0
m-3,1
P
P
P
P
P
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
P
4,1
6,0
5,1
7,0
minimum vertical blanking requirement = 4
m,2
m,1
P
P
P
P
P
P
00 00 00 ............................................................................................. 00 00 00
00 00 00 ............................................................................................. 00 00 00
m-2,2
4,2
6,1
m-3,2
P
5,2
7,1
P
m,2
m,1
VALID IMAGE - Even Field
VALID IMAGE - Odd Field
P
P
P
P
4,3
6,2
5,3
7,2
.....................................P
.....................................P
.....................................P
.....................................P
Field Blanking = R0xBF, bits 7:0
.....................................P
.....................................P
.....................................P
.....................................P
VERTICAL BLANKING
m-2,n-2
m,n-1
m-3,n-1
m,n-1
4,n-1
6,n-1
5,n-1
7,n-1
P
P
m,n
P
P
P
m,n
P
P
P
56
4,n
6,n
m-2,n
5,n
7,n
m-3,n
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
FIELD BLANKING
HORIZONTAL
BLANKING
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
Feature Description
(EQ 16)
(EQ 17)
(EQ 18)

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