mt9v032 aptina, mt9v032 Datasheet - Page 14

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 4:
Table 5:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Parameter
Parameter
A+Q
V
Nrows x (A + Q)
F
V’
F”
Frame Time (continued)
Frame Time—Long Integration Time
Notes:
Name
Name
Row time
Vertical blanking
Frame valid time
Total frame time
Vertical blanking (long
integration time)
Total frame time (long integration
exposure time)
Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to
Figure 7 on page 14). The recommended master clock frequency is 26.66 MHz. The
vertical blanking and total frame time equations assume that the number of integration
rows (bits 11 through 0 of R0x0B) is less than the number of active rows plus blanking
rows minus overhead rows (R0x03 + R0x06 - 2). If this is not the case, the number of inte-
gration rows must be used instead to determine the frame time, as shown in Table 5. In
this example it is assumed that R0x0B is programmed with 523 rows. For Simultaneous
Mode, if the exposure time register (0x0B) exceeds the total readout time, then vertical
blanking is internally extended automatically to adjust for the additional integration
exposure time required. This extended value is not written back to R0x06 (vertical
blanking). R0x06 can be used to adjust frame to frame readout time. This register does
not affect the exposure time but it may extend the readout time.
1. The MT9V032 uses column parallel analog-to-digital converters, thus short row timing is not possible.
The minimum total row time is 660 columns (horizontal width + horizontal blanking). The minimum
horizontal blanking is 43. When the window width is set below 617, horizontal blanking must be
increased. The frame rate will not increase for row times less than 660 columns.
Equation
(Number of Master Clock Cycles)
(R0x0B + 2 - R0x03) × (A + Q) + 4
(R0x0B + 2) × (A + Q) + 4
Equation
R0x04 + R0x05
(R0x06) x (A + Q) + 4
(R0x03) × (A + Q)
V + (Nrows x (A + Q))
15
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
Default Timing at 26.66 MHz
846 pixel clocks
= 846 master
= 31.72μs
38,074 pixel clocks
= 38,074 master
= 1.43ms
406,080 pixel clocks
= 406,080 master
= 15.23ms
444,154 pixel clocks
= 444,154 master
= 16.66ms
Default Timing
at 26.66 MHz
38,074 pixel clocks
= 38,074 master
= 1.43ms
444,154 pixel clocks
= 444,154 master
= 16.66ms
©2005 Aptina Imaging Corporation. All rights reserved.
Output Data Format