mt9v032 aptina, mt9v032 Datasheet - Page 61

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Propagation Delays for FRAME_VALID and LINE_VALID Signals
Figure 35:
Figure 36:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Propagation Delays for PIXCLK and Data Out Signals
Propagation Delays for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same rising master clock
edge as the data output. The LINE_VALID goes HIGH on the same rising master clock
edge as the output of the first valid pixel's data and returns LOW on the same master
clock rising edge as the end of the output of the last valid pixel's data.
As shown in the “Output Data Timing” on page 14, FRAME_VALID goes HIGH 143 pixel
clocks before the first LINE_VALID goes HIGH. It returns LOW 23 pixel clocks after the
last LINE_VALID goes LOW.
FRAME_VALID
D
OUT
SYSCLK
LINE_VALID
PIXCLK
(9:0)
PIXCLK
t
PD
t
t
P
PLH
FLR
t
P
SD
t
F
62
FRAME_VALID
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
LINE_VALID
PIXCLK
t
HD
t
R
Aptina reserves the right to change products or specifications without notice.
t
P
FLF
©2005 Aptina Imaging Corporation. All rights reserved.
Electrical Specifications