lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 31

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

10.3.3 Output data switching (SDIN, RDATA)
• RDATA outputs demodulation data when the PLL is locked, and outputs SDIN input data when the PLL is unlocked.
• When SDIN input data is selected, switch to a clock source synchronized to the SDIN data.
• With the RDTSTA setting, the SDIN input data is output to RDATA regardless of the locked/unlocked status of the
• With the RDTMUT setting, the RDATA output data can be also muted forcibly.
• Even when the clock source is set to XIN with OCKSEL and RCKSEL, the PLL continues operating as long as the
This output is automatically switched according to the PLL locked/unlocked status. For details, see the timing charts
below.
PLL.
PLL is not stopped with PLLOPR. At this time, the PLL status is continuously output from RERR unless error output
is forcibly set with RESTA. Moreover, the processed information can be read with the microcontroller interface
regardless of the PLL status.
PLL status
PLL status
RDATA
RDATA
RERR
RERR
CKST
CKST
CKSTP=0
CKSTP=0
Figure 10.10 Timing Chart of RDATA Output Data Switching
Demodulation data
UNLOCK
SDIN data
LOCK
LC89058W-E
(a): Lock-in stage
(b): Unlock stage
LOCK
Muted
UNLOCK
Muted
Demodulation data
SDIN data
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