lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 33

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

10.4 Error Output Processing
10.4.1 Lock error and data error output (RERR)
• RERR outputs an error flag when a PLL lock error or a data error occurs.
• It is possible to treat non-PCM data reception as an error by the RESEL setting.
• The RERR output conditions are set with RESTA. Since the PLL status can be output at all times, the PLL status can
10.4.2 PLL lock error
• The PLL gets unlocked for input data that lost bi-phase modulation regularity, or input data for which preambles B, M,
• RERR turns to “H” when the PLL lock error occurs and returns to “L” when the data demodulation returns normal
• The rising and falling edges of RERR are synchronized with RLRCK.
10.4.3 Input data parity error
• Odd number of errors among parity bits in input data and input parity errors are detected.
• If an input parity error occurs 9 or more times in succession, RERR turns to "H" indicating that the PLL is locked, and
• The error flag output format can be selected with REDER, when an input parity error is output less than 8 times in
10.4.4 Other errors
• Even if RERR turns to "L", the channel status bits of 24 to 27 (sampling frequency) are always fetched and the data of
• The PLL causes a lock error when the fs changes as described above. However, in order to support sources with a
• If a setting which regard non-PCM data input as an error is made with RESEL, RERR turns to “H” when non-PCM
In the FSERR setting, when the PLL is locked, RERR is turned to “L” without reflecting the fs calculation result to the
Moreover, the data comparison at the channel status bits of 24 to 27 as described above is not performed.
error flag concerning input data within reception range by FSLIM [1:0].
and W cannot be detected. However, even if preambles B, M, and W are detected if the timing does not conform to
the IEC60958, the PLL get unlocked and processed. For example, period of preamble B is not every192 frames.
and “H” is held for somewhere between 3ms to 144ms. This holding time is determined with the ERWT[1:0] setting.
the previous block is compared with the current data. Moreover, the input data sampling frequency is calculated from
the fs clock extracted from the input data, and the fs calculated value is compared in a same way as described above.
If any difference is detected in these data, RERR is instantly made "H" and the same processing as for PLL lock errors
is carried out.
variable fs (for example a CD player with a variable pitch function), it is possible to set with FSERR not to output an
error flag unless fs changes exceeding the PLL capture range.
data input is detected. At this time, the PLL locked status and various output clocks are subject to the input data, but
the output data is muted.
after holding "H" for somewhere between 3ms and 144ms, it returns to "L".
succession.
be always monitored, even when the clock source is XIN.
LC89058W-E
No.A1056-33/64