lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 44

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

• Don’t do the setting to which RMCK=3.072MHz is output by XRSEL [1:0]=10(1/4 output) setting when
• Setting of XRBCK [1:0] relate to setting of RMCK output clock. RBCK output clock is set to become 1/2 or less of
XIN=12.288MHz is input because it doesn't satisfy the output setting condition of RBCK and SBCK.
RMCK output clock at XIN source.
PRSEL [1:0]
XRSEL [1:0]
XRBCK [1:0]
XRLRCK [1:0]
XRLRCK1
DI15
DI7
0
XRLRCK0
Setting of RMCK output frequency while PLL is locked
(enabled when PLLACC is set to “0”)
Setting of RMCK output frequency during XIN source
Setting of RBCK output frequency during XIN source
Setting of RLRCK output frequency during XIN source
DI14
DI6
0
CCB address: 0xE8; Command address: 3; R system output clock setting
00: 512fs×1/2 (256fs) (initial value)
01: 512fs×1/1 (512fs)
10: 512fs×1/4 (128fs)
11: Muted
00: 1/1 of XIN input frequency (initial value)
01: 1/2 of XIN input frequency
10: 1/4 of XIN input frequency
11: Muted
00: 3.072MHz output (RMCK≥6.144MHz) (initial value)
01: 6.144MHz output (RMCK≥12.288MHz)
10: 12.288MHz output (RMCK=24.576MHz)
11: Muted
00: 48kHz output (initial value)
01: 96kHz output
10: 192kHz output
11: Muted
XRBCK1
DI13
DI5
1
XRBCK0
LC89058W-E
DI12
DI4
1
XRSEL1
DI11
DI3
0
XRSEL0
DI10
DI2
0
PRSEL1
CAU
DI1
DI9
No.A1056-44/64
PRSEL0
CAL
DI0
DI8