w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 17

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.11
The Serial Interface Bus (SIB)
The Serial Interface Bus (SIB) is configured as a token passing Local Area Network, and is intended
for inter-chip communications in parallel processing applications. The Serial Interface Bus has four
pins associated with its use:
information). The SIB has seven (7) registers associated with its use: STATE, SR0, SR1, SR2, SR3,
SCSR, and BAR.
1.11.1 The STATE Register
($0022)
ACSR
The STATE register is a read-only register that provides the host processor with the timing
state of the SIB (see Figure 1-13 for more information on activities during each timing state).
The STATE register is the decoded output of a "state machine" that counts up from 0 to 37
and then back to 0 on positive transitions of SCLK. Only one decoded output is asserted at a
time. STATE has the same value at the same time in all devices and is used to synchronize
message transfer. It is reset to State 0 upon system RESET.
STATE is normally read only during manufacturing test. A read of the state register can
produce invalid results if the SCLK is not synchronous with the processor clock. When the
SCLK is enabled on the chip with its MPU, it is always synchronized with the SIB.
Receiver Error Flag
7
Software Semiphore
6
Figure 1-9 ACSR Bit Assignments
CHIN CHOUT, SDAT, and SCLK (see Section 2.19 for more
Receiver Enable
5
Odd or Even Parity Select
4
Parity Enable
3
Seven or Eight Bit Data Select
2
Transmitter Interrupt Source Select
1
Transmitter Enable
0
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