w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 7

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.6
The Timers
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
A write to the Timer 1, 2 or A high counter writes to the timer hi latch and this sequence
occurs: 1.6.6.1
Upon Timer clock input negative edge the timer low counter is decremented by 1.
When T1 or T2 prescaler mode is enabled, (making timer low counter a divide-by-N+1
prescaler) then timer low counter is reloaded from timer low latch. Monitor Timer M does not
have a prescaler mode.
A write to the timer low counter writes the timer low latch.
A read of the timer high or low counter reads the timer high or low counter.
Upon Timer clock input negative edge when the timer low counter reaches zero, the timer
high counter is decremented by 1. Upon Timer clock input positive edge, when the timer high
counter reaches zero, this sequence occurs:
1.6.5.1
1.6.5.2
1.6.6.2
Timer M is disabled after RESB and is activated by the first Timer Control Register One
(TCR10) transition from "0" to "1" (the first load of Timer M).
1.6.7.1
Timer 1 and 2 set their associated interrupt flag. If the interrupt is enabled the
MPU is then interrupted and control is transferred to the vector associated with
the interrupt. When Timer M times out, the W65C134S is restarted: on-chip
logic pulls RESB pin low for 2 CLK cycles and releases RESB to go high,
"restarting" the W65C134S.
The timer hi counter is loaded from the timer hi latch, and timer low counter is
loaded from timer low latch.
The timer low counter is loaded from the timer low latch, and the timer hi
counter is loaded from the timer hi latch.
The Timer M counter is reloaded with the value in the Timer M latches when the
TCR10 bit 0 makes a transition from a "0" to "1". TCR10 transition from a "1" to
a "0" has no effect on the timer.
The timer hi latch is loaded from data bus.
7