w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 41

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

3.3
AC Characteristics
Timing
Parameter
tISA
tIHA
tODA
tOHA
tISD
tIHD
tODD
tOHD
tISB
tIHB
tODSY
tISRR
tIHRR
tODRN
tOHRN
tISP
tIHP
tODP
tOHP
tISI
tIHI
tISS
tIHS
tODS
tOHS
tISC
tIHC
tODC
tOHC
tISU
tIHU
tODU
tOHU
tODD (DMA)
tODPH
tODSC
tODCSR
tODCSF
tR
tF
tBR
tBV
CEXT
tCYC
tPWL
tPWH
tCYC2
tPWL2
tPWH2
tCYCF
tPWLF
tPWHF
Table 3-3 AC Characteristics
Address input setup from PHI2
Address input hold from PHI2
Address output delay from PHI2
Address output hold from PHI2
Data input setup from PHI2
Data input hold from PHI2
Data output delay from PHI2
Data output hold from PHI2
BE input setup from PHI2
BE input hold from PHI2
SYNC output delay from PHI2
RDY/RESB input setup from PHI2
RDY/RESB input hold from PHI2
RUN output delay from PHI2
RUN output hold from PHI2
Port input setup from PHI2
Port input hold from PHI2
Port output delay from PHI2
Port output hold from PHI2
Interrupt input setup from PHI2
Interrupt input hold from PHI2
Serial Data input setup from SCLK
Serial Data input hold from SCLK
Serial Data output delay from SCLK
Serial Data output hold from SCLK
Chain input setup from SCLK
Chain input hold from SCLK
Chain output delay from SLCK
Chain output hold from SCLK
UART Data input setup from PHI2
UART Data input hold from PHI2
UART Data output delay from PHI2
UART Data output hold from PHI2
Data output delay from PHI2 (ROM read)
PHI2 output delay from CLK/FCLK
SCLK output delay from PHI2
CS output delay from PHI2 rising
CS output delay from PHI2 falling
FCLK/CLK risetime
FCLK/CLK falltime
BE to RESB
BE to D0-7, A0-15, WEB Valid
External Capactive load
CLK cycle time
CLK low time
CLK high time
PHI2 cycle time
PHI2 low time
PHI2 high time
FCLK cycle time
FCLK low time
FCLK high time
Definition
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