w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 22

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.11.4.5
1.11.4.6
1.11.4.7
1.11.4.8
1. Any device that had "read pending" (SCSR4=1) just before transition to
2. While in state 3-34 (STATE=$08) the device that is master sends its
3. Any device that does not have "deaf" SCSR5 set, including the master,
4. SCLK advances the state counter to state 35 (STATE=$10).
State 35 events (STATE=$10)
The SIB is prepared for acknowledgement. State 35 (STATE=$10) is for
the master to insure that SDAT is high on entry to state 36 (STATE=$20).
The device that is master outputs a high level on SDAT. SCLK advances
the state counter to state 36 (STATE=$20).
State 36 events (STATE=$20)
The receive should acknowledge its receipt of the message in state 36
(STATE=$20). When asserted, the destination device (the device that has
SR37,SR36,SR35 equal to BAR2,BAR1,BAR0 and "deaf" SCSR5=0) pulls
SDAT low to acknowledge reception to the master. SCLK advances the
state counter to state 37 (STATE=$40).
State 37 events (STATE=$40)
The MPU's are interrupted with the result of transmission in the SR's. State
37 (STATE=$40) is for the master to interrupt and signal its processor if the
message it sent was not acknowledged, for the receiver to interrupt and
signal its processor that a message is available to read, and for the master
to insure that SDAT is high on transition to state 0 (STATE=$01). In state
37 (STATE=$40) the following occurs:
1. If the master saw SDAT high just before the transition to state 37
2. The device with SCSR5=0 that has the SR37,6,5=BAR2,1,0 (message
3. The master outputs a high level on SDAT for the duration of state 37
4. SCLK advances the state counter to state 0 (STATE=$01).
Message processing may now be performed by the receiver. The message
is read by the receiver's processor in response to the SIB interrupt (SIBIRQ)
generated by SCSR4 "read pending", by reading the message in its shift
register, and when finished clears SCSR4 "read pending" (on the trailing
edge of the read of SR3).
The message may now be processed.
The next message may now be sent on the SIB.
state 3 sets "deaf" SCSR5, so that it cannot receive the incoming
message on top of the one its processor has not read.
shift-register data output onto SDAT.
advances its shift register, on SCLK positive transitions, thus acquiring
the data that was in the master's shift-register.
(STATE=$40) (meaning there was no acknowledgement) then it sets
SCSR3 "message not acknowledged" to interrupt and signal its
processor that the message was not received. If the master saw SDAT
low just before the transition to state 37 (STATE=$40) (meaning there
was acknowledgement) then SCSR3 is cleared and does not interrupt
its processor.
with its address), sets SCSR4 "read pending" to interrupt and signal its
processor that a message is pending.
(STATE=$40).
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