w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 5
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w65c134s
Manufacturer Part Number
w65c134s
Description
W65c134s 8-bit Microcontroller
Manufacturer
Western Design Center, Inc.
Datasheet
1.W65C134S.pdf
(60 pages)
E xternal ROM Enable
U
0 = internal ROM at $F000-FFFF
1 = external ROM at $F000-FFFF
7
N MIB, IRQ1B and IRQ2B Input Enable
U
0 = Pins 40-42 are standard I/O
1 = P40=NMIB, P41=IRQ1B, P42=IRQ2B inputs
6
P ort 54-57 Edge Sensitive Interrupt Input Enable
U
0 = No EDGE interrupt inputs on P54-57
1 = EDGE interrupt inputs on P54-57
5
P ort 50-53 Edge Sensitive Interrupt Input Enable
U
0 = No EDGE interrupt inputs on P50-53
1 = EDGE interrupt inputs on P50-53
4
I n-Circuit-Emulation (ICE) Enable
U
0 = RUN = RUN and W65C134S is in normal mode of operation
1 = RUN and all on chip addressed memory or I/O for reads or writes
are output on the data bus (this is the emulation mode of operation)
3
S erial Interface Bus (SIB) Enable
U
0 = SIB Disabled
1 = SIB Enabled P64=SCLK, P65=SDAT, P66=CHIN,
P67=CHOUT and enable SIB interrupt
2
P ort 44-47 Edge Sensitive Interrupt Input
U
Enable
0 = No Edge Interrupt Inputs on P44-47
1 = Edge Interrupt Inputs on P44-47
1
E xternal Memory Bus Enable
U
1 = Ports 0,1,2 are address and
data bus for external memory or
I/O access
= Ports 0,1,2 are I/0
0
BCR ($001B)
5
0
U