w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 37

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.10 Address Bus (Axx)
Ports 0 and 1 are also the address bus A0-A15 when configured by the Bus Control Register (BCR). (See
section 1.4 for BCR mode selection.) When BCR0 and BCR7 are set to "1" and BCR3=0 (normal operating
mode) for external memory addressing, Axx are all "1's" when addressing on-chip memory. When BCR3=1
(ICE mode), the address bus is always active so that the ICE can trace internal read and write operations.
2.11 Data Bus (Dx)
Port 2 is the data bus D0-D7 when configured by the Bus Control Register (BCR). (See section 1.4 for BCR
mode selection.) When BCR0 and BCR7 are set to a "1" and BCR3=0 (normal operating mode) for external
memory addressing, Dx are all "1's" when addressing on-chip memory. When BCR3=1 (ICE mode), the
data bus is always active so that the ICE can trace internal read and write operations. During external
memory cycles the data bus is in the Hi-Z state during PHI2 low time.
2.12 Positive Edge Interrupt inputs (PExx)
Port pins P44, P45, P50, P51, P54, P55, and P56 have the Positive Edge sensitive interrupt inputs (PE44,
PE45, PE50, PE51, PE54, PE55, and PE56) multiplexed with the I/O. When the pin is enabled as an edge
interrupt (as defined by the Bus Control Register (BCR)), an interrupt is generated, and the associated bit is
set (by an internal one-shot circuit) in the Interrupt Flag Register (IFRx) on a positive transition from "0" to
"1". The transition from "1" to "0" has no effect on the IFR. When the associated Interrupt Enable Register
bit (IERx) is set to a "1", the MPU will be interrupted provided the interrupt flag bit in the MPU status register
P (I flag) is cleared to a "0". When the I flag is "1", interrupts are disabled.
2.13 Negative Edge Interrupt inputs (NExx)
Port pins P46, P47, P52, P53, and P57 have the Negative Edge sensitive interrupt inputs (NE46, NE47,
NE52, NE53, and NE57) multiplexed with the I/O. When the pin is enabled as an edge interrupt (as defined
by the Bus Control Register (BCR)), an interrupt is generated, and the associated bit is set (by an internal
one-shot circuit) in the Interrupt Flag Register (IFRx) on a negative transition from "1" to "0". The transition
from "0" to "1" has no effect on the IFR. When the associated Interrupt Enable Register bit (IERx) is set to a
"1", the MPU will be interrupted provided the interrupt flag bit in the MPU status register P (I flag) is cleared
to a "0". When I equals a "1", interrupts are disabled.
2.14 Chip Select outputs (active low) (CSxB)
The CSxB Chip Select outputs are enabled (individually) as outputs on Port 3 with the PCS3x (Port 3 Chip
Select register). Chip select 7, CS7B, is also automatically enabled by BCR7=1. Each of the eight chip
selects is dedicated to one block of external memory; the mapping of each chip select to external addresses
is given in Table 1-3 System Memory Map. Chip selects CS3B, CS4B, CS5B, CS6B, and CS7B are
considered "clocked" chip selects. This means that they only become active during PHI2 high time. Chip
selects CS0B, CS1B, and CS2B are "not clocked," and are active anytime the address bus is in the
appropriate memory block.
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