w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 36

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.6
and the chip goes into the static low power state.
disables all input buffers. The inputs will not float due to the bus holding devices. Inputs that are unaffected
by RESB are BE and WEB.
$89 if BE is low or to $00 if BE is high. The MPU then begins the power-up reset interrupt sequence in
which the program counter is loaded with the reset vector that points to the first instruction to be executed.
(See WDC's W65C02 microprocessor data sheet for more information and instruction timing.)
out", Timer M times out causing a system Reset. (See section 1.5, The Timers for more information.)
2.7
VDD is the positive power supply and has a range given in Table 3-4.
2.8
VSS is the system logic ground. All voltages are referenced to this supply pin.
2.9
Reset Input/Output RESB ( RESB)
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
Positive Power Supply (VDD)
Internal Logic Ground (VSS)
I/O Port Pins ( Pxx)
2.9.1
2.9.2
these bidirectional Ports has a port data register (PDx) and port data direction register
(PDDx). A zero ("0") in PDDxx defines the associated I/O pin as an input with the output
transistors in the "off" high impedance state. A one ("1") in PDDxx defines the I/O pin as an
output. A read of PDx always reads the pin. After reset, all Port pins become input pins with
both the data and data direction registers reset to 0. The inputs will not float due to the bus
holding devices.
(CSxB); this register is defined in Table 1-3 System Memory Map. A "1" in bit x of PCS3
enables Chip Select CSxB to be output over P3x while a "0" in PCS3x specifies the value in
the output data register is to be output on P3x. Port 3 data register is set to all "1's" after
Reset, and PCS3 is
enabled.
When RESB is low for 2 or more processor PHI2 cycles all activity on the W65C134S stops
After a Reset, all I/O pins become inputs. Because of NOR gates on the inputs, RESB
When RESB goes from low to high, RUN goes high, the Bus Control Register is initialized to
The reset sequence takes 9 cycles to complete before loading the first instruction opcode.
RESB is a bidirectional pin which is pulled low internally for "restarting" due to a "monitor time
All ports, except Port 3, which is an output only Port, are bidirectional I/O ports. Each of
Port 3 has an associated Chip Select register (PCS3) that is used to enable Chip Selects
cleared to all "0's" after RESET, except if BCR7=1 then CS7B is
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