RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 15

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.5
4.6
ALU
The RM7000 has two complete integer ALUs each consisting of an integer adder/subtractor, a
logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution
unit. Each of these units is optimized to perform all operations in a single processor cycle.
Table 3
Integer Multiply/Divide
The RM7000 has a single dedicated integer multiply/divide unit optimized for high-speed multiply
and multiply-accumulate operations. The multiply/divide unit resides in the F type execution unit.
Table 4 shows the performance of the multiply/divide unit on each operation.
Table 4 Integer Multiply/Divide Operations
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo (
In addition to the baseline MIPS IV integer multiply instructions, the RM7000 also implements the
3-operand multiply instruction, MUL. This instruction specifies that the multiply result go directly
to the integer register file rather than the Lo register. The portion of the multiply that would have
normally gone into the Hi register is discarded. For applications where it is known that the upper
half of the multiply result is not required, using the MUL instruction eliminates the necessity of
executing an explicit MFLO instruction.
Also included in the RM7000 are the multiply-add instructions MAD/MADU . This instruction
multiplies two operands and adds the resulting product to the current contents of the Hi and Lo
registers. The multiply-accumulate operation is the core primitive of almost all signal processing
Unit
Adder
Logic
Shifter
Opcode
MULT/U,
MAD/U
MUL
DMULT,
DMULTU
DIV, DIVD
DDIV,
DDIVU
ALU Operations
Operand
Size
16 bit
32 bit
16 bit
32 bit
any
any
any
F Pipe
add, sub
logic, moves, zero shifts
(nop)
non zero shift
Latency
4
5
4
5
9
36
68
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Repeat
Rate
3
4
3
4
8
36
68
M Pipe
add, sub, data address
add
logic, moves, zero shifts
(nop)
non zero shift, store align
MFHI
Stall
Cycles
0
0
2
3
0
0
0
/
MFLO
) instructions.
Released
15