RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 38

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
Mode bit
0
4..1
7..5
8
10..9
11
12
14..13
15
Table 16 Boot Time Mode Stream
Description
reserved (must be zero)
Write-back data rate
SysClock to Pclock Multiplier
Mode bit 20 = 0 / Mode bit 20 = 1
Specifies byte ordering. Logically ORed with
BigEndian input signal.
Non-Block Write Control
Timer Interrupt Enable/Disable
Enable the external tertiary cache
Output driver strength - 100% = fastest
External Tertiary cache RAM type:
0:
1:
2:
3:
4:
5:
6:
7:
8:
9-15: reserved
0:
1:
2:
3:
4:
5:
6:
7:
0:
1:
00:
01:
10:
11:
0:
1:
0:
1:
00:
01:
10:
11:
0:
1:
DDDD
DDxDDx
DDxxDDxx
DxDxDxDx
DDxxxDDxxx
DDxxxxDDxxxx
DxxDxxDxxDxx
DDxxxxxxDDxxxxxx
DxxxDxxxDxxxDxxx
Multiply by 2/x
Multiply by 3/x
Multiply by 4/x
Multiply by 5/2.5
Multiply by 6/x
Multiply by 7/3.5
Multiply by 8/x
Multiply by 9/4.5
Little endian
Big endian
R4000 compatible non-block writes
reserved
pipelined non-block writes
non-block write re-issue
Enable the timer interrupt on IP[5]
Disable the timer interrupt on IP[5]
Disable
Enable
67% strength
50% strength
100% strength
83% strength
Dual-cycle deselect (DCD)
Single-cycle deselect (SCD)
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Mode bit
17..16
19..18
20
23..21
24
25
26
255..27
Description
System configuration identifiers - software visible
in processor Config[21..20] register
Reserved: Must be zero
Pclock to SysClock multipliers.
Reserved: Must be zero
JTLB Size.
On-chip secondary cache control.
Enable two outstanding reads with out-of-order
return
Reserved: Must be zero
0:
1:
0:
1:
0:
1:
0:
1:
48 dual-entry
64 dual-entry
Integer multipliers (2,3,4,5,6,7,8,9)
Half integer multipliers (2.5,3.5,4.5)
Disable
Enable
Disable
Enable
Released
38