RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 40

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
Table 18
SysADC(7:0)
SysCmd(8:0)
SysCmdP
SysClock
VccP
VssP
Pin Name
Pin Name
Clock/control interface Pins
Type
Input/Output
Input/Output
Input/Output
Type
Input
Input
Input
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Description
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
System Command/Data Identifier Bus Parity
For the RM7000, unused on input and zero on output.
Description
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to
VccInt through a filter circuit.
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to
VssInt through a filter circuit.
System address/data check bus
System command/data identifier bus
System clock
Released
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