RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 26

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.22 Cache Locking
4.23 Cache Management
Table 6 Cache Attributes
The RM7000 allows critical code or data fragments to be locked into the primary and secondary
caches. The user has complete control over what locking is performed with cache line granularity.
For instruction and data fragments in the primaries, locking is accomplished by setting either or
both of the cache lock enable bits in the CP0 ECC register, specifying the set via a field in the CP0
ECC register, and then executing either a load instruction or a Fill_I cache operation for data or
instructions respectively. Only two sets are lockable within each cache: set A and set B. Locking
within the secondary works identically to the primaries using a separate secondary lock enable bit
and the same set selection field. As with the primaries, only two sets are lockable: sets A and B.
Table 7 summarizes the cache locking capabilities.
Table 7 Cache Locking Control
To improve the performance of critical data movement operations in the embedded environment,
the RM7000 significantly improves the speed of operation of certain critical cache management
Attribute
Size
Associativity
Replacement
Algorithm.
Line size
Index
Tag
Write policy
read policy
read order
write order
miss restart
following:
Parity
Cache
Primary I
Primary D
Secondary
Lock Enable
ECC[27]
ECC[26]
ECC[25]
Instruction
16KB
4-way
cyclic
32 byte
vAddr
pAddr
n.a.
n.a.
critical word first
NA
complete line
per word
11..0
35..12
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Set Select
ECC[28]=1 B
ECC[28]=1 B
ECC[28]=1 B
ECC[28]=0 A
ECC[28]=0 A
ECC[28]=0 A
Data
16KB
4-way
cyclic
32 byte
vAddr
pAddr
write-back, write-
through
non-blocking (2
outstanding)
critical word first
sequential
first double (if
waiting for data)
per byte
11..0
35..12
Activate
Fill_I
Load/Store
Fill_I or
Load/Store
Secondary
256KB
4-way
cyclic
32 byte
pAddr
pAddr
block write-back,
bypass
non-blocking (data
only, 2 outstanding)
critical word first
sequential
n.a.
per doubleword
15..0
35..16
Tertiary
512K, 1M, 2M, 4M,
or 8M
direct mapped
direct replacement
32 byte
pAddr
pAddr
block write-through,
bypass
non-blocking (data
only, 2 outstanding)
critical word first
sequential
n.a.
per byte
22..0
35..19
Released
26