RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 32

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.31 Enhanced Write Modes
4.32 External Requests
4.33 Test/Breakpoint Registers
The “Hint” field of the data prefetch instruction is used to specify the action taken by the
instruction. The instruction can operate normally (that is, fetching data as if for a load operation) or
it can allocate and fill a cache line with zeroes on a primary data cache miss.
Like previous MIPS processor designs, the RM7000 implements two enhancements to the original
R4000 write mechanism: Write Reissue and Pipeline Writes. In write reissue mode, a write rate of
one write every two bus cycles can be achieved. A write issues if WrRdy* is asserted two cycles
earlier and is still asserted during the issue cycle. If it is not still asserted then the last write will
reissue. Pipelined writes have the same two bus cycle write repeat rate, but can issue one
additional write following the deassertion of WrRdy*.
The RM7000 can respond to certain requests issued by an external device. These requests take one
of two forms: Write requests and Null requests. An external device executes a write request when it
wishes to update one of the processors writable resources such as the internal interrupt register. A
null request is executed when the external device wishes the processor to reassert ownership of the
processor external interface. Typically a null request will be executed after an external device, that
has acquired control of the processor interface via ExtRqst*, has completed an independent
transaction between itself and system memory in a system where memory is connected directly to
the SysAD bus. Normally this transaction would be a DMA read or write from the I/O system.
To increase both observability and controllability of the processor thereby easing hardware and
software debugging, a pair of Test/Break-point, or Watch, registers, Watch1 and Watch2, have
been added to the RM7000. Each Watch register can be separately enabled to watch for a load
address, a store address, or an instruction address. All address comparisons are done on physical
addresses. An associated register, Watch Mask, has also been added so that either or both of the
Watch registers can compare against an address range rather than a specific address. The range
granularity is limited to a power of two.
When enabled, a match of either Watch register results in an exception. If the Watch is enabled for
a load or store address then the exception is the Watch exception as defined for the R4000 with
Cause exception code twenty-three. If the Watch is enabled for instruction addresses then a newly
defined Instruction Watch exception is taken and the Cause code is sixteen. The Watch register
which caused the exception is indicated by Cause bits 25..24. Table 9 summarizes a Watch
operation.
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
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