RM7000-300S PMC [PMC-Sierra, Inc], RM7000-300S Datasheet - Page 18

• Manufacturer Part Number: RM7000-300S
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
4.11 System Control Coprocessor Registers
The RM7000 incorporates all system control coprocessor (CP0) registers internally. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM7000 includes registers to
implement a real-time cycle counting facility, to aid in cache and system diagnostics, and to assist
in data error detection.
To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7000,
both the data and control register spaces of CP0 are supported by the RM7000. In the data register
space, that is the space accessed using the MFC0 and MTC0 instructions, the RM7000 supports
the same registers as found in the RM5200, R4000 and R5000 families. In the control space, that is
the space accessed by the previously unused CTC0 and CFC0 instructions, the RM7000 supports
five new registers. The first three of these new 32-bit registers support the enhanced interrupt
handling capabilities and are the Interrupt Control, Interrupt Priority Level Lo (IPLLO), and
Interrupt Priority Level Hi (IPLHI) registers. These registers are described further in the section on
interrupt handling. The other two registers, Imprecise Error 1 and Imprecise Error 2, have been
added to help diagnose bus errors which occur on non-blocking memory references.
Figure 5 shows the CP0 registers.
Figure 5 CP0 Registers
LLAddr
17*
47
0
TagLo
28*
(entries protected
from TLBWR)
Used for memory
management
TLB
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
TagHi
29*
Random
* Register number
Config
Wired
Index
PRId
Info
15*
16*
0*
1*
6*
7*
Watch2
Status
EPC
ECC
12*
14*
19*
26*
Used for exception
processing
CacheErr
ErrorEPC
XContext
Watch1
Cause
13*
18*
20*
27*
30*
Watch Mask
Released
24*
18