lxt9785 Intel Corporation, lxt9785 Datasheet - Page 111

• Manufacturer Part Number: lxt9785
• Description: Advanced 8-port 10/100 Mbps Phy Transceivers
• Manufacturer: Intel Corporation

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 39. Intel
Designation
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
BGA15 Ball
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
®
M10,
C1,
N9,
L9,
M9
K8
F1
B3
P9
LXT9785 BGA15 Signal Descriptions (Sheet 5 of 7)
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
AMDIX_EN
LINKHOLD
FIFOSEL1
FIFOSEL0
Symbol
LED0_1
LED0_2
CFG_1
CFG_2
CFG_3
I, ST, ID
I, ID, ST
I, ID, ST
OD, TS,
I, ST, IP
SL, IP
Type
LED Signal Descriptions
Signal Description
Auto MDI/MDIX Enable Default.
This pin is read at startup or reset. Its value at that time is
used to set the default state of Register bit 27.9 for all ports.
These register bits can be read and overwritten after
startup / reset. Refer to
When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports. When
inactive (Low) MDIX is selected according to the MDIX pin.
Global Port Configuration Defaults 1-3.
These pins are read at startup or reset. Their value at that
time is used to set the default state of register bits shown in
Table 42, “Intel® LXT9785/9785E Global Hardware
Configuration Settings” on page 129
register bits can be read and overwritten after startup /
reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports (refer
to
FIFO Select <1:0>.
These pins are read at startup or reset. Their value at that
time is used to set the default state of Register bits
18.15:14 for all ports. These register bits can be read and
overwritten after startup/reset.
These pins are shared with RMII-RxER<5:4>. An external
pull-up resistor (see applications section for value) can be
used to set FIFO Select<1:0> to active while RxER<5:4>
are three-stated during hardware reset. If no pull-up is
used, the default FIFO select state is set via the internal
pull-down resistors.
See
Depth Configurations” on page
LINKHOLD Default. This pin is read at startup or reset. Its
value at that time is used to set the default state of Register
bit 0.11 for all ports. This register bit can be read and
overwritten after startup / reset. When High, the LXT9785/
9785E powers down all ports.
This pin is shared with RMII-RxER6. An external pull-up
resistor (see applications section for value) can be used to
set LINKHOLD active while RxER6 is three-stated during
H/W reset. If no pull-up is used, the default LINKHOLD
state is set inactive via the internal pull-down resistor.
Port 0 LED Drivers 1-2.
These pins drive LED indicators for Port 0. Each LED can
display one of several available status conditions as
selected by the LED Configuration Register (refer to
Table 96, “LED Configuration Register (Address 20, Hex
14)” on page 213
page 129
Table 36, “Intel® LXT9785/LXT9785E Receive FIFO
for details).
for details).
Table 40 on page
97.
for all ports. These
119.
113