lxt9785 Intel Corporation, lxt9785 Datasheet - Page 4

no-image

lxt9785

Manufacturer Part Number
lxt9785
Description
Advanced 8-port 10/100 Mbps Phy Transceivers
Manufacturer
Intel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
lxt9785EHC
Quantity:
320
Part Number:
lxt9785EHC D0
Quantity:
353
Part Number:
lxt9785EHC DO
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
lxt9785HC
Quantity:
6
Part Number:
lxt9785HC
Manufacturer:
LEVELONE
Quantity:
20 000
Part Number:
lxt9785HC C2
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
lxt9785HCB2
Manufacturer:
Intel
Quantity:
184
Part Number:
lxt9785MBC
Manufacturer:
INTEL
Quantity:
1 500
Contents
4
4.4
4.5
4.6
4.7
4.8
4.9
4.3.7
4.3.8
4.3.9
4.3.10 Global Hardware Control Interface ...................................................................... 124
4.3.11 FIFO Initial Fill Values.......................................................................................... 124
Operating Requirements................................................................................................... 125
4.4.1
4.4.2
Initialization ....................................................................................................................... 126
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
Link Establishment............................................................................................................ 129
4.6.1
Serial MII Operation.......................................................................................................... 132
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
RMII Operation ................................................................................................................. 141
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
100 Mbps Operation ......................................................................................................... 145
MDIO Management Interface .............................................................................. 121
MII Sectionalization.............................................................................................. 123
MII Interrupts........................................................................................................ 123
Power Requirements ........................................................................................... 125
Clock/SYNC Requirements ................................................................................. 125
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
4.4.2.5
MDIO Control Mode............................................................................................. 126
Hardware Control Mode....................................................................................... 126
Power-Down Mode .............................................................................................. 127
4.5.3.1
4.5.3.2
Reset ................................................................................................................... 128
Hardware Configuration Settings......................................................................... 129
Auto-Negotiation .................................................................................................. 129
4.6.1.1
4.6.1.2
4.6.1.3
4.6.1.4
4.6.1.5
4.6.1.6
SMII Reference Clock.......................................................................................... 135
TxSYNC Pulse (SMII/SS-SMII)............................................................................ 135
Transmit Data Stream.......................................................................................... 135
4.7.3.1
4.7.3.2
Receive Data Stream........................................................................................... 136
4.7.4.1
4.7.4.2
4.7.4.3
4.7.4.4
Collision ............................................................................................................... 136
Source Synchronous-Serial Media Independent Interface .................................. 137
RMII Reference Clock.......................................................................................... 141
Transmit Enable................................................................................................... 142
Carrier Sense & Data Valid.................................................................................. 142
Receive Error....................................................................................................... 142
Out-of-Band Signaling ......................................................................................... 142
4B/5B Coding Operations .................................................................................... 142
Reference Clock .................................................................................. 125
TxCLK Signal (SS-SMII only)............................................................... 125
TxSYNC Signal (SMII/SS-SMII)........................................................... 125
RxSYNC Signal (SS-SMII only) ........................................................... 125
RxCLK Signal (SS-SMII only) .............................................................. 126
Global (Hardware) Power Down .......................................................... 128
Port (Software) Power Down ............................................................... 128
Base Page Exchange .......................................................................... 129
Manual Next Page Exchange .............................................................. 130
Controlling Auto-Negotiation ................................................................ 130
Link Criteria.......................................................................................... 130
Parallel Detection................................................................................. 131
Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode .......................................................... 131
Transmit Enable................................................................................... 135
Transmit Error ...................................................................................... 135
Carrier Sense....................................................................................... 136
Receive Data Valid .............................................................................. 136
Receive Error ....................................................................................... 136
Receive Status Encoding..................................................................... 136
Revision Date: August 28, 2003
Document Number: 249241
Revision Number: 007
Datasheet

Related parts for lxt9785