lxt9785 Intel Corporation, lxt9785 Datasheet - Page 89

• Manufacturer Part Number: lxt9785
• Description: Advanced 8-port 10/100 Mbps Phy Transceivers
• Manufacturer: Intel Corporation

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 32. Intel
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
2. The IP/ID resistors are disabled during hardware power-down mode.
BGA23
L17,
M2,
M3,
L16
L15
N1,
L4,
N2
K1
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
Designation
®
Ball/Pin
LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 2 of 4)
PQFP
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
178
177
176
88
89
90
91
92
83
MODESEL_1
MODESEL_0
AMDIX_EN
SECTION
Symbol
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
I, ST, ID
I, ST, ID
I, ST, ID
I, ST, IP
Type
1
Signal Description
Address <4:0>.
Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY
address.
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0].
00 = RMII
01 = SMII
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all RMII, SMII, or SS-SMII.
Sectionalization Select.
This pin selects sectionalization into separate ports.
0 = 1x8 ports,
1 = 2x4 ports
Auto MDI/MDIX Enable Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.9 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
“Intel® LXT9785/LXT9785E MDIX Selection” on
page
When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports.
When inactive (Low) MDIX is selected according to the
MDIX pin.
119.
2
Table 40
91