lxt9785 Intel Corporation, lxt9785 Datasheet - Page 130

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lxt9785

Manufacturer Part Number
lxt9785
Description
Advanced 8-port 10/100 Mbps Phy Transceivers
Manufacturer
Intel Corporation
Datasheet

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.7
132
Table 43. Intel
Serial MII Operation
The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial
MII (SMII). The SMII performs the following functions:
The Serial MII operates at 125 MHz using a global reference clock and frame synchronization
signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and
RxDatan). All signals are synchronous to REFCLK.
Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B
coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new
data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times.
TxData
SYNC
RxData
REFCLK
1. Refer to
Signal
Signal Descriptions – PQFP” on page 39
descriptions.
Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.
Allows a multi-port MAC/PHY communication with one system clock.
Operates in both half and full-duplex.
Supports per-packet switching between 10 Mbps and 100 Mbps data rates.
®
LXT9785/LXT9785E SMII Signal Summary
Table 7, “Intel® LXT9785/LXT9785E SMII Specific
PHY
PHY
MAC
MAC &
PHY
To
MAC
MAC
PHY
System
From
Transmit data & control
Synchronization
Receive data & control
Synchronization
for detailed signal
Purpose
Table 43
summarizes the SMII signals.
Revision Date: August 28, 2003
Document Number: 249241
Revision Number: 007
Datasheet

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