lxt9785 Intel Corporation, lxt9785 Datasheet - Page 207

• Manufacturer Part Number: lxt9785
• Description: Advanced 8-port 10/100 Mbps Phy Transceivers
• Manufacturer: Intel Corporation

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 1 of 2)
1. R = Read Only, LH = Latching High – cleared when read.
2. The default values are updated on completion of reset and reflect the status or change in status at that
3. The default value is determined by the default value of Register bit 0.12.
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a
Bit
15
14
13
12
11
10
9
8
7
6
5
time. Intel recommends that the register status be read on completion of reset.
the pin(s) are latched at startup or hardware reset.
Pause hardware configuration pin. The default for the BGA15 package is 0.
Name
Reserved
10/100 Mode
Transmit Status
Receive Status
Collision Status
Link
Duplex Mode
Auto-Negotiation
Auto-Negotiation
Complete
FIFO Error
Polarity
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Description
Write as 0, ignore on Read
0 = The LXT9785/LXT9785E is operating in 10 Mbps
1 = The LXT9785/LXT9785E is operating in 100 Mbps
NOTE: The status is valid for TX and FX operation.
0 = The LXT9785/LXT9785E is not transmitting a packet
1 = The LXT9785/LXT9785E is transmitting a packet
0 = Packet has not been received since last read
1 = Packet has been received since last read
0 = A collision is not occurring
1 = A collision is occurring
NOTE: This bit is set when jabber is detected, regardless
0 = Link is down
1 = Link is up
0 = Half-duplex
1 = Full-duplex
0 = The LXT9785/LXT9785E is in manual mode
1 = The LXT9785/LXT9785E is in auto-negotiation mode
This signal is based upon Register bit 0.12.
0 = Auto-negotiation process is not complete
1 = Auto-negotiation process is complete
0 = No FIFO error occurred
1 = FIFO error occurred (overflow or underflow)
0 = Polarity is not reversed
1 = Polarity is reversed
NOTE: During 100 Mbps operation, this bit is not valid
mode
mode
of duplex.
and may vary. Auto MDIX activity may increase
the variability.
Type
LH
LH
LH
LH
R
R
R
R
R
R
R
R
R
R
R
1
Default
Note 3
0
0
0
0
0
0
0
0
0
0
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