gc41c501g1-so24i CORERIVER Semiconductor, gc41c501g1-so24i Datasheet - Page 29

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gc41c501g1-so24i

Manufacturer Part Number
gc41c501g1-so24i
Description
4-bit Microcontrollers With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
ADDRESS
Mnemonic
Power Supply
System Clock
Write /Erase
6.12. In Application Programming (IAP)
Electrical Characteristic of IAP
Information Region
Parameter
Frequency
Voltage
Time
Note that the program time depends on the
configuration of system clock frequency.
If the system clock frequency is out of IAP range,
user need to change F
configuring CKCFG SFR.
The first byte contains CFGWD
May be used to store user ID, or checksum, etc.
Only the full chip erase function of ISP can erase this
region.
CFGWD
0
Symbol
F
V
Tp
SYS
DD
1
MIN
2.7
1.5
5
2
SYS
before and after IAP by
3
TYP
2.0
8
-
4
MAX
5.5
3.3
5
11
6
MHz
Unit
ms
V
7
0x000
0x3FF
FLASH Regions
CFGWD : Configuration Word
EEPROM area is a part of program memory.
CFGWD[0] (ISP_LOCK) : Disable read, write, or
erase by ISP except the full chip erase.
CFGWD[1] (IAP_RE) : Enable read by IAP.
CFGWD[2] (IAP_PE) : Enable write or erase by
IAP.
1 K Byte
FLASH
ATOM1.0 Family
0x3FF
0x3C0
0x1C0
0x000
0x1FF
Preliminary
EEP1
EEP0
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