gc41c501g1-so24i CORERIVER Semiconductor, gc41c501g1-so24i Datasheet - Page 48

• Manufacturer Part Number: gc41c501g1-so24i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

JNB bit, rel
Appendix A : Instruction Set (13/19)
L_BIT_ZERO:
Binary Code
Description
Carry Flag
Operation
Example
Cycles
Bytes
Branches if the bit in data memory is 0.
The address of memory is given by DPTR and
bit position is given by two least significant bits
of opcode .
The branch destination is computed by adding
the signed relative-displacement in the
second byte of the instruction to the PC, after
incrementing the PC to the start of the next
instruction. The contents of memory is not
affected.
(PC) ← (PC) + 2
IF M[DP].bit = 0 THEN (PC) ← (PC) + rel
Not affected.
2
2
JNB 3, L_BIT_ZERO
......
......
1001
10bb
; IF M[DP].3 = 1
; IF M[DP].3 = 0
rrrr
rrrr
JNC rel
Binary Code
L_C_ZERO:
Description
Carry Flag
Operation
Example
Cycles
Bytes
Branches if the carry flag is 0.
The branch destination is computed by adding
the signed relative-displacement in the
second byte of the instruction to the PC, after
incrementing the PC to the start of the next
instruction.
(PC) ← (PC) + 2
IF (C) = 0 THEN (PC) ← (PC) + rel
Not affected.
2
2
JNC L_C_ZERO
......
......
1001
ATOM1.0 Family
0110
; IF (C) = 1
; IF (C) = 0
rrrr
Preliminary
rrrr
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