ST10F271E STMICROELECTRONICS [STMicroelectronics], ST10F271E Datasheet
ST10F271E
Related parts for ST10F271E
ST10F271E Summary of contents
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... Up to 111 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis) ■ Idle, power down and stand-by modes ■ Single voltage supply: 5V ±10% Rev 1 ST10F271B ST10F271E TQFP144 ( 1.4mm) (Thin Quad Flat Package) 1/180 www.st.com 1 ...
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... Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Flash non volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 37 Flash non volatile access protection register Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . Flash non volatile access protection register 1 high 39 ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E 5.5.6 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 45 6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3 Alternate and selective boot mode (ABM and SBM 6.3.1 6.3.2 6.3.3 7 Central processing unit (CPU 7.1 Multiplier-accumulator unit (MAC 7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3 MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8 External bus controller ...
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... System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 20.3 Synchronous reset (warm reset 20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4/180 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E 21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 21.2.1 21.2.2 21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 21.3.1 21.3.2 21.3.3 21.3.4 22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 111 23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 23.2 XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 24 ...
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... Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 173 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6/180 Phase Locked Loop (PLL 149 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2. Summary of IFLASH address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3. Address space reserved to the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. Flash modules sectorization (Read operations Table 5. Flash modules sectorization (Write operations or with ROMS1=’1’ or BootStrap mode)27 Table 6. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. ...
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... CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 80. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 81. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 82. SSC slave mode timings 174 Table 83. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 84. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8/180 = 5V ± ST10F271B/ST10F271E = –40 to +125° 153 ...
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... ST10F271B/ST10F271E List of figures Figure 1. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Pin configuration (top view Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4. ST10F271 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value Figure 5. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 6. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 7. CPU block diagram (MAC Unit not included Figure 8. ...
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... External bus arbitration (releasing the bus 171 Figure 60. External bus arbitration (regaining the bus 172 Figure 61. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 62. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 63. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 64. TQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10/180 ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E 1 Introduction The ST10F271B and ST10F271E devices are derivatives of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. These two derivatives slightly differ on the available RAM size and Analog Channel Input number. These points will be highlighted in the corresponding chapters. For all information that is common to the 2 derivatives, the generic ST10F271 name will be used ...
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... Logic symbol 12/180 XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT V AREF V AGND ST10F271 NMI STBY READY ALE WRL Port 5 16-bit ST10F271B/ST10F271E Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD ...
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... P8.7 / TxD1 / CC23IO VDD VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3 P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 *: AN16 to AN23 are only available for the ST10F271E ST10F271 19 20 ...
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... CAPCOM2: CC20 capture input / compare output P8.5 CC21IO CAPCOM2: CC21 capture input / compare output P8.6 CC22IO CAPCOM2: CC22 capture input / compare output RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous) P8.7 CC23IO CAPCOM2: CC23 capture input / compare output ASC1: Clock / Data output TxD1 (Asynchronous/Synchronous) ST10F271B/ST10F271E Function ...
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... ST10F271B/ST10F271E Table 1. Pin description (continued) Symbol Pin Type 19-26 I P7.0 - P7.7 ... ... I/O ... ... 26 I/O 27-36 I 39- P5 P5.10 - P5. 47-54 I/O 57-64 47 I/O ... ... P2.0 - P2.7 54 I/O P2.8 - P2.15 I ... ... I 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers ...
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... ASC0: clock / data output (asynchronous/synchronous) P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous) BHE External memory high byte enable signal P3.12 WRH External memory high byte write strobe P3.13 SCLK0 SSC0: master clock output / slave clock input System clock output (programmable divider on CPU P3.15 CLKOUT clock) ST10F271B/ST10F271E Function ...
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... ST10F271B/ST10F271E Table 1. Pin description (continued) Symbol Pin Type 85-92 I P4.0 –P4 WR/WRL 96 O READY READY ALE 98 O Port 8-bit bidirectional I/O port bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state ...
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... Data path width 8-bit P0L.0 – P0L.7: D0 – D7 P0H.0 – P0H.7: I/O Multiplexed bus modes Data path width 8-bit P0L.0 – P0L.7: AD0 – AD7 P0H.0 – P0H.7: 8 – A15 A ST10F271B/ST10F271E Function turned off) to bias the 32 DD 16- D15 16-bi AD0 - AD7 D8 - AD15 A DD ...
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... PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS). Only for the ST10F271E – The pins of P1L also serve as the additional ( analog input channels for the A/D converter, where P1L.x equals ANy (Analog input channel y, where 16) ...
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... Digital supply voltage = + 5V during normal operation, idle and power down modes. It can be turned off when Stand-by RAM mode is selected. Digital ground 1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest V ST10F271B/ST10F271E Function pin. SS ...
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... ST10F271B/ST10F271E 3 Functional description The architecture of the ST10F271 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F271. Figure 3. Block diagram XRAM 16 2K ...
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... SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is 22/180 Chapter 5: Internal Flash memory on User Mode Not visible 00’0000h - 00’1FFFh 00’2000h - 00’3FFFh 00’4000h - 00’5FFFh 00’6000h - 00’7FFFh 01’8000h - 01’FFFFh 02’0000h - 02’FFFFh 03’0000h - 03’FFFFh / RESERVED 04’0000h - 04’FFFFh / RESERVED ST10F271B/ST10F271E Size 32K 64K 64K 64K ...
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... The XRAM1 (2K Bytes) address range is 00’E000h - 00’E7FFh if enabled. The XRAM2 (4K Bytes) address range is after reset 09’0000h - 09’1FFFh and is mirrored every 16KByte boundary. ST10F271E XRAM: 8K+2K Bytes of XRAM The XRAM1 (2K Bytes) address range is 00’E000h - 00’E7FFh if enabled. The XRAM2 (16K Bytes) address range is after reset 09’0000h - 09’3FFFh and is mirrored every 16KByte boundary ...
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... CPU clock. No tristate waitstate is used. The following set of features are provided: ● CLKOUT programmable divider ● XBUS interrupt management registers ● ADC multiplexing on P1L register (only for ST10F271E) ● Port1L digital disable register for extra ADC channels ● CAN2 multiplexing on P4.5/P4.6 ● CAN1-2 main clock prescaler ● ...
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... ST10F271B/ST10F271E Figure 4. ST10F271 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value) Code Page Segment Segment FF FFFF 1023 11 FFFF 255 17 Ext. Memory 11 0000 10 FFFF 16 Ext. Memory 10 0000 0F FFFF XRAM2 XRAM2 15 XRAM2 XRAM2 0F 0000 0E FFFF XRAM2 XRAM2 14 XRAM2 XRAM2 0E 0000 XRAM2 0D FFFF XRAM2 ...
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... Registers Bank 0: 128 Kbyte Program Memory + Program/Erase 8 Kbyte Test-Flash I-BUS Interface Addresses 0x00 0000 to 0x02 FFFF 1) 0x03 0000 to 0x04 FFFF 2) 0x05 0000 to 0x07 FFFF 0x08 0000 to 0x08 FFFF ST10F271B/ST10F271E HV and Ref. Generator Controller Size 128 Kbyte 128 Kbyte 192 Kbyte 64 Kbyte ...
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... ST10F271B/ST10F271E mapping. Accesses to this address range will send back the content of the Flash cell (by default FFFFh, blank value when the device is delivered) 2 Accesses to the area will send back the value 009Bh. 5.2.2 Modules structure The IFLASH module is composed by a bank (Bank 0) of 256 Kbyte of Program Memory divided in 8 sectors (B0F0 ...
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... DFB0 - 0x0008 DFB1 0x0008 DFB8 - 0x0008 DFB9 0x0008 DFBC - 0x0008 DFBF 0x0000 EB50 - 0x0000 EB51 2 byte ST10F271B/ST10F271E Bus Addresses Size size 8 byte 8 byte 4 byte 2 byte 2 byte 16-bit ...
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... ST10F271B/ST10F271E 5.3 Write operation The Flash module have one single register interface mapped in the memory space of the IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L) ...
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... FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY0 bit is reset. 30/180 FCR reserved ST10F271B/ST10F271E Reset Value: 0000h res. res. LOCK R Function : ...
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... ST10F271B/ST10F271E 5.4.2 Flash control register 0 high The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low (FCR0L) is used to enable and to monitor all the write operations on the IFLASH. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only ...
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... Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of a Write operation if no errors are detected. 32/180 FCR reserved B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0 RS ST10F271B/ST10F271E Function Reset value ...
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... ST10F271B/ST10F271E 5.4.4 Flash control register 1 high The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low (FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank. FCR1H (0x08 0006 reserved Table 10. ...
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... FCR FCR ST10F271B/ST10F271E Reset value Function Reset value Function Reset value ...
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... ST10F271B/ST10F271E 5.4.9 Flash address register low FARL (0x08 0010 ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Table 16. Flash address register low Bit Address 15:2 These bits must be written with the Address of the Flash location to program in the ADD(15:2) following operations: Word Program (32-bit) and Double Word Program (64-bit). In Double Word Program bit ADD2 must be written to ‘ ...
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... In case of multiple Sector Erase, the not protected sectors are erased, while the protected sectors are not erased and bit WPF is set. This bit has to be software reset. 36/180 FCR WPF RESER SEQER RC RC ST10F271B/ST10F271E Reset value reserved 10ER PGER ERER Function 0000h ...
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... ST10F271B/ST10F271E 5.5 Protection strategy The protection bits are stored in Non Volatile Flash cells inside IFLASH module, that are read once at reset and stored in 4 Volatile registers. Before they are read from the Non Volatile cells, all the available protections are forced active during reset. ...
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... Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. 38/180 NVR reserved NVR ST10F271B/ST10F271E Reset value: ACFFh Function Delivery value:: FFFFh Function 1 0 DBGP ACCP RW ...
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... ST10F271B/ST10F271E 5.5.5 Flash non volatile access protection register 1 high FNVAPR1H (0x08 DFBE PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 Table 22. Flash non volatile access protection register 1 high Bit Protections Enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit PEN15-0 ACCP is enabled again ...
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... TAUB in XFVTAUR0. 40/180 Read XRAMS or Read IFLASH / Ext Mem / Jump to Jump to IFLASH XRAM or Ext Mem Yes / Yes Yes / Yes No / Yes Yes / Yes No / Yes Yes / Yes No / Yes Yes / Yes ST10F271B/ST10F271E Read FLASH Write FLASH Registers Registers Yes No Yes No Yes No Yes No Section 5.5.9 ). ...
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... ST10F271B/ST10F271E 5.6 Write operation examples In the following, examples for each kind of Flash write operation are presented. Note: The write operation commands must be executed from another memory (internal RAM or external memory ST10F269 device. In fact, due to IBus characteristics not possible to perform write operation in Flash while fetching code from Flash. ...
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... SUSP in FCR0H*/ /*Set SER in FCR0H*/ /*Operation resume*/ /*Set SER in FCR0H*/ /*Set B0F1*/ /*Operation start*/ /*Set SUSP in FCR0H*/ /*Loop to wait for LOCK=0 and WMS=0*/ /*Rst SUSP in FCR0H*/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Operation start*/ ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E A Sector Erase can be suspended by setting SUSP bit. ● To perform a Word Program operation during Erase Suspend, firstly bits SUSP and SER must be reset, then bit WPG and WMS can be set. ● To resume the Sector Erase operation bit SER must be set again. ...
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... Operation Word Program (32-bit) Double Word Program (64-bit) Sector Erase Set Protection Program/Erase Suspend 44/180 . Select bit Address and data FARL/FARH WPG FDR0L/FDR0H FARL/FARH DWPG FDR0L/FDR0H FDR1L/FDR1H SER FCR1L/FCR1H SPR FDR0L/FDR0H SUSP None ST10F271B/ST10F271E Start bit WMS WMS WMS WMS None ...
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... ST10F271B/ST10F271E 6 Bootstrap loader ST10F271 implements Boot capabilities in order to: ● Support bootstrap via UART or bootstrap via CAN for the standard bootstrap. ● Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different way. 6.1 Selection among user-code, standard or selective bootstrap The boot modes are triggered with a special combination set on Port0L[5...4]. Those signals, as other configuration signals, are latched on the rising edge of RSTIN pin. ● ...
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... P0L.4 low at reset), additional check is made. Depending on the value at the User key location, following behavior will occur: ● A jump is performed to the Standard Bootstrap Loader ● Only UART is enabled for bootstraping ● Only CAN1 is enabled for bootstraping ● The device enters an infinite loop. 46/180 ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E 7 Central processing unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F271’s instructions can be executed in one instruction cycle which requires 31 ...
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... Shared with standard ALU 48/180 Operand signed/unsigned Multiplier Concatenation 32 Mux Sign Extend MRW Scaler 0h 08000h Repeat Unit Mux 40 MCW A 40-bit Signed Arithmetic Unit MSW Flags MAE Control Unit ST10F271B/ST10F271E Operand Mux MAH MAL 40 8-bit Left/Right Shifter ...
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... ST10F271B/ST10F271E 7.2 Instruction set summary The Table 26 lists the instructions of the ST10F271. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 26. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) ...
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... Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation ST10F271B/ST10F271E Bytes ...
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... ST10F271B/ST10F271E 7.3 MAC co-processor specific instructions The Table 27 lists the MAC instructions of the ST10F271. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 Bytes. Table 27. MAC instruction set summary Mnemonic ...
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... The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. 52/180 ST10F271B/ST10F271E ...
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... ST10F271B/ST10F271E 9 Interrupt system The interrupt response time for internal program execution is from 78ns to 187.5ns at 64 MHz CPU clock. The ST10F271 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC) ...
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... T1IE T1INT T7IR T7IE T7INT T8IR T8IE T8INT T2IR T2IE T2INT T3IR T3IE T3INT T4IR T4IE T4INT T5IR T5IE T5INT ST10F271B/ST10F271E Vector Trap Location Number 00’0058h 16h 00’005Ch 17h 00’0060h 18h 00’0064h 19h 00’0068h 1Ah 00’006Ch 1Bh 00’0070h 1Ch 00’0074h 1Dh 00’ ...
Page 55
... ST10F271B/ST10F271E Table 28. Interrupt sources (continued) Source of Interrupt or PEC Service Request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 See Paragraph 9.1 9.1 See Paragraph See Paragraph 9 ...
Page 56
... ASC1 Receive ASC1 Transmit ASC1 Transmit Buffer 56/180 7 0 XIR x SEL[7: Flag[7:0] XIR x SEL[15: Enable[7: XP0INT ST10F271B/ST10F271E XP1INT XP2INT XP3INT ...
Page 57
... ST10F271B/ST10F271E Table 29. X-Interrupt detailed mapping (continued) ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0 9.2 Exception and error traps list Table 30 shows all of the possible exceptions or error conditions that can arise during run- time. Table 30. Trap priorities Exception Condition Reset Functions: Hardware Reset ...
Page 58
... TxI when using a 40 MHz and 64 MHz CPU clock are listed in the Table 32 and The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures. 58/180 , for the timer input selector Tx, are determined as a function of the Tx Table 33 respectively. ST10F271B/ST10F271E ...
Page 59
... ST10F271B/ST10F271E Table 31. Compare modes Compare Modes Interrupt-only compare mode; several compare interrupts per timer period are Mode 0 possible Pin toggles on each compare match; several compare events per timer period are Mode 1 possible Interrupt-only compare mode; only one compare interrupt per timer period is ...
Page 60
... Timer Input Selection T2I / T3I / T4I 000b 001b 010b 011b 1.25 5MHz 2.5MHz 625 kHz MHz ST10F271B/ST10F271E 100b 101b 110b 128 256 512 312.5 156.25 78.125 39.1 kHz kHz kHz kHz 111b ...
Page 61
... ST10F271B/ST10F271E Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz MHz CPU Resolution Period 13.1ms maximum Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz MHz CPU Pre-scaler factor Input Freq Resolution Period maximum Figure 10. Block diagram of GPT1 ...
Page 62
... Timer Input Selection T5I / T6I 000b 001b 010b 011b 8MHz 4MHz 2MHz 62.5ns 125ns 250ns 0.5µs 4.1ms 8.2ms 16.4ms 32.8ms ST10F271B/ST10F271E 100b 101b 110b 64 128 256 312.5 156.25 625 kHz kHz kHz 1.6µs 3.2µs 6.4µs 104.8ms 209.7ms 419.4ms 838.9ms 100b 101b 110b ...
Page 63
... ST10F271B/ST10F271E Figure 11. Block diagram of GPT2 T5EUD CPU Clock T5IN CAPIN T6IN CPU Clock T6EUD T5 2n n=2...9 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode 2n n=2...9 Control General purpose timer unit U/D Interrupt Request Interrupt Request Reload Interrupt Request Toggle FF T60TL ...
Page 64
... ST10F271B/ST10F271E show the PWM frequencies for different * Match * Up/Down/ Clear Control Match Output Control Enable Write Control * 12-bit 14-bit 9.77 kHz 2.44Hz 152.6Hz 38 ...
Page 65
... ST10F271B/ST10F271E 13 Parallel ports 13.1 Introduction The ST10F271 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F271 has nine groups of I/O lines gathered as follows: ● Port two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte) ● ...
Page 66
... Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. 66/180 ST10F271B/ST10F271E 2 C ...
Page 67
... ST10F271B/ST10F271E This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data ...
Page 68
... The ST10F271B has 16 multiplexed input channels on Port 5. The ST10F271E has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. ...
Page 69
... ST10F271B/ST10F271E register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. ● Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated ...
Page 70
... ST10F271B/ST10F271E ) is supported in this mode. CPU CPU S0BRS = ‘1’ MHz CPU Reload Value 0.0% / 0.0% +6.3% / -7.0% +6.3% / -0.8% +3.3% / -1.4% +0 ...
Page 71
... ST10F271B/ST10F271E Table 41. ASC asynchronous baud rates by reload value and deviation errors (f S0BRS = ‘0’, f CPU Baud Rate (Baud) Deviation Error 2 000 000 0.0% / 0.0% 112 000 +1.5% / -7.0% 56 000 +1.5% / -3.0% 38 400 +1.7% / -1.4% 19 200 +0.2% / -1.4% 9 600 +0.2% / -0.6% 4 800 +0.2% / -0.2% 2 400 +0.2% / 0.0% 1 200 0.1% / 0.0% 600 0.0% / 0.0% 300 0.0% / 0.0% 245 0.0% / 0.0% Note: The deviation errors given in the errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency). ...
Page 72
... Table 42 and Table 43 ST10F271B/ST10F271E CPU S0BRS = ‘1’ MHz CPU Reload Value 600 0.0% / 0.0% 407 0.0% / 0.0% CPU S0BRS = ‘1’ MHz CPU Reload Value ...
Page 73
... ST10F271B/ST10F271E Table 44 and Table 45 the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8Mbaud. Table 44. SSC synchronous baud rate and reload values (f Baud Rate Reserved Can be used only with f lower) 6.6M Baud 5M Baud 2.5M Baud 1M Baud 100K Baud ...
Page 74
... C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I 2 Fast I C mode (100 to 400 kHz). 74/180 2 C Bus specification. The bus modes are supported interface may be selected between Standard mode (0 to 100 kHz) and ST10F271B/ST10F271E 2 C Module can ...
Page 75
... ST10F271B/ST10F271E 17 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers ...
Page 76
... Figure 14. Connection to single CAN bus via common CAN transceivers +5V 2.7kW CAN_H CAN_L 76/180 Figure 13 . CAN1 CAN2 P4.5 P4.6 P4.4 P4.7 CAN CAN Transceiver Transceiver CAN bus Figure 14 CAN1 CAN2 P4.5 P4.6 P4.4 P4 CAN Transceiver CAN bus ST10F271B/ST10F271E XMISC.CANPAR = 0 . Thanks to the OR-Wired XMISC.CANPAR = Open Drain Output ...
Page 77
... ST10F271B/ST10F271E Multiple CAN bus The ST10F271 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 15 Figure 15. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel Mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 16 . Figure 16. Connection to one CAN bus with internal Parallel Mode enabled 1 ...
Page 78
... Vice versa, when at power on and after Reset, the 32 kHz is not present, the main STBY oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Stand-by mode, while in Power Down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled). 78/180 ST10F271B/ST10F271E ...
Page 79
... ST10F271B/ST10F271E 19 Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. ...
Page 80
... Status PONR Low Low LHWR High SHWR High 3) WDTR 3) SWR for more details on minimum reset pulse duration. 20.6 and ). ST10F271B/ST10F271E Table 48 Conditions Power- > RSTIN t > (1032 + 12) TCL + max(4 TCL, RSTIN 500ns) t > max(4 TCL, 500ns) RSTIN ≤ (1032 + 12) TCL + max(4 TCL, ...
Page 81
... ST10F271B/ST10F271E 20.2 Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F271 is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins ...
Page 82
... V and ground: the internal 1.8V drivers are sized to drive 18 currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Electrical Characteristics Section). and 18 Asynchronous Power-on timing diagrams are reported, ST10F271B/ST10F271E pin should 18 ...
Page 83
... ST10F271B/ST10F271E Figure 17. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST ≤ 1.2 ms (for resonator oscillation + PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) ≤ 2 TCL ... ≥ ≤ 500 ns 3 ...
Page 84
... It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures It occurs when RSTIN is low and RPD is detected (or becomes) low as well. 84/180 ST10F271B/ST10F271E ≥ 1.2 ms (for resonator oscillation + PLL stabilization) ≥ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization ...
Page 85
... ST10F271B/ST10F271E Figure 19. Asynchronous hardware RESET ( RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (internal) FLARST RST Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500ns to take into account of Input Filter on RSTIN pin 1) ≥ ≤ 500 ns ≥ ≤ ...
Page 86
... Note that this bit is always cleared on power-on or after a reset sequence. 86/180 1) ≥ ≤ 500 ns not transparent transparent not transparent transparent not transparent system start-up configuration . ST10F271B/ST10F271E 2) 3..8 TCL ≥ ≤ 500 ns 3..4 TCL not t. not t. not t. 8 TCL Latching point of Port0 for Section 20.1 for ...
Page 87
... ST10F271B/ST10F271E Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts 1024 TCL cycles long: at the end of it, and after other 8 TCL the level of RSTIN is sampled (after the filter, see RSTF in the drawings already at high level, only Short Reset is flagged (Refer to recognized still low, the Long reset is flagged as well ...
Page 88
... For a Software or Watchdog reset events, an active synchronous reset is completed regardless of the RPD status important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter). 88/180 Figure 19 . There is no effect if RPD comes again above ST10F271B/ST10F271E ...
Page 89
... ST10F271B/ST10F271E Figure 21. Synchronous short / long hardware RESET ( ≤ 4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD Notes: 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered ...
Page 90
... TCL 200mA Discharge ST10F271B/ST10F271E ≥ ≤ 500 ns not t. not t. 3..8 TCL3) 8 TCL 8 TCL At this time RSTF is sampled HIGH or LOW SHORT or LONG reset 2) VRPD > 2.5V Asynchronous Reset not entered ...
Page 91
... ST10F271B/ST10F271E Figure 23. Synchronous long hardware RESET ( RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT RPD Notes during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. Even if RPD returns above the threshold, the reset is defnitively taken as asynchronous ...
Page 92
... TCL At this time RSTF is sampled LOW LONG reset 200 µ A Discharge ST10F271B/ST10F271E 3..4 TCL not t. not t. not t. 3) 3..8 TCL 8 TCL 1) V > 2.5V Asynchronous Reset not entered RPD ...
Page 93
... ST10F271B/ST10F271E Refer to next Figures 29 for bidirectional. 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY READY is sampled active (low) after the programmed wait states ...
Page 94
... TCL periods (minimum time to recognize a Short Hardware reset) after the reset exiting (refer to or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. 94/180 ST10F271B/ST10F271E not transparent not t. transparent not transparent not transparent not t ...
Page 95
... ST10F271B/ST10F271E The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL). ...
Page 96
... System reset Figure 27 WDT bidirectional RESET (EA=1) RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT 96/180 ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not transparent ≤ 1024 TCL ST10F271B/ST10F271E not t. not t. ≤ 2 TCL 7 TCL ...
Page 97
... ST10F271B/ST10F271E Figure 28 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT ≥ ≤ 500 ns not transparent transparent not t. not transparent not t. not transparent 1024 TCL At this time RSTF is sampled HIGH WDT Reset is flagged in WDTCON ...
Page 98
... TCL Figure The input RSTIN provides an internal pull-up device equalling a resistor of ST10F271B/ST10F271E ≥ ≤ 500 ns not t. not t. 8 TCL At this time RSTF is sampled LOW so HW Reset is entered . The RSTIN pin provides an internal pull-up ...
Page 99
... ST10F271B/ST10F271E To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason recommended to connect the external R0-C0 circuit shown in Figure 30 to the RPD pin. On power-up, the logical low level on RPD pin forces an asynchronous hardware reset when RSTIN is asserted low ...
Page 100
... EINIT Instruction Clr Q Set Reset State Machine Clock SRST instruction Trigger watchdog overflow Clr Reset Sequence (512 CPU Clock Cycles) Asynchronous Reset From/to Exit Powerdown Circuit ST10F271B/ST10F271E External Reset Source RSTOUT V DD BDRSTEN V DD Weak Pulldown (~200µA) RSTIN ...
Page 101
... ST10F271B/ST10F271E 20.8 Reset application examples Next two timing diagrams ( bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 33. Example of software or watchdog bidirectional reset ( Figure 33 and Figure 34 ) provides additional examples of ...
Page 102
... System reset Figure 34. Example of software or watchdog bidirectional reset ( 102/180 ST10F271B/ST10F271E ...
Page 103
... ST10F271B/ST10F271E 20.9 Reset summary A summary of the different reset events is reported in the table below. Table 49. Reset event Event Asynch. Power-on Reset Asynch Asynch Asynch. Hardware Reset (Asynchronous Asynch Asynch Synch Synch. Short Hardware ...
Page 104
... PORT0 latched in RP0H, SYSCON ST10F271B/ST10F271E WDTCON Flags max Section 20.3 for details). PORT0 ...
Page 105
... ST10F271B/ST10F271E Figure 35. PORT0 bits latched into the different registers after reset H.7 H.6 CLKCFG RP0H CLKCFG Clock Generator P0L.7 ROMEN 10 9 PORT0 H.5 H.4 H.3 H.2 H.1 H.0 L.7 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Port 4 Port 6 Logic Logic P0L.7 SYSCON BYTDIS WRCFG L.6 L.5 L.4 L.3 L.2 L.1 L.0 BSL Res. ADP EMU Bootstrap Loader ...
Page 106
... There are two different operating Power Down modes: protected mode and interruptible mode. 106/180 ) can be turned off while a portion of the internal RAM remains DD dedicated power pin. , holding the MCU under reset state. DD ST10F271B/ST10F271E ...
Page 107
... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16Kbytes for ST10F271E), the RTC counters and 32 kHz on- chip oscillator amplifier. Chapter 20: System reset on page 80 ...
Page 108
... V 18 internal reference. It could happen that a high level of RAM write strobe lower than V ): The bus status could contain a valid address 18 18SB ST10F271B/ST10F271E is on) the V pin can be tied to V STBY (see in particular the 32 kHz STBY can contribute to increase this ...
Page 109
... ST10F271B/ST10F271E Warning: 21.3.2 Exiting stand-by mode After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V internal reference (derived from V 18SB It is recommended to held the device under RESET (RSTIN pin forced low) until external V voltage pin is stable ...
Page 110
... ST10F271B/ST10F271E , a summary of the different off run off biased on run on biased off off off biased on on off biased on off on biased off off off biased ...
Page 111
... ST10F271B/ST10F271E 22 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON possible to program the clock prescaling factor: in this way on P3 ...
Page 112
... CAPCOM register 0 interrupt control register 41h CAPCOM register 1 BDh CAPCOM register 1 interrupt control register 42h CAPCOM register 2 BEh CAPCOM register 2 interrupt control register 43h CAPCOM register 3 BFh CAPCOM register 3 interrupt control register ST10F271B/ST10F271E Reset value - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0xx0h ...
Page 113
... ST10F271B/ST10F271E Table 52. List of special function registers (continued) Physical Name address CC4 FE88h CC4IC b FF80h CC5 FE8Ah CC5IC b FF82h CC6 FE8Ch CC6IC b FF84h CC7 FE8Eh CC7IC b FF86h CC8 FE90h CC8IC b FF88h CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC ...
Page 114
... CAPCOM Mode Control register 6 94h CAPCOM Mode Control register 7 08h CPU Context Pointer register B5h GPT2 CAPREL interrupt control register 04h CPU Code Segment Pointer register (read only) 80h P0L direction control register ST10F271B/ST10F271E Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h ...
Page 115
... ST10F271B/ST10F271E Table 52. List of special function registers (continued) Physical Name address DP0H b F102h E DP1L b F104h E DP1H b F106h E DP2 b FFC2h DP3 b FFC6h DP4 b FFCAh DP6 b FFCEh DP7 b FFD2h DP8 b FFD6h DPP0 FE00h DPP1 FE02h DPP2 FE04h DPP3 FE06h EMUCON FE0Ah EXICON b F1C0h E EXISEL ...
Page 116
... CPU program status word 18h PWM module up/down counter 0 19h PWM module up/down counter 1 1Ah PWM module up/down counter 2 1Bh PWM module up/down counter 3 18h PWM module pulse width register 0 ST10F271B/ST10F271E Reset value - - 00h - - 00h FFFFh - - 00h - - 00h - - 00h - - 00h 0000h ...
Page 117
... ST10F271B/ST10F271E Table 52. List of special function registers (continued) Physical Name address PW1 FE32h PW2 FE34h PW3 FE36h PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E QR0 F004h E QR1 F006h E QX0 F000h E QX1 F002h E RP0H b F108h E S0BG FEB4h S0CON b FFB0h S0EIC b FF70h S0RBUF FEB2h S0RIC ...
Page 118
... Watchdog timer register (read only) D7h Watchdog timer control register 0Eh XPER address select register 3 Section 9.1 C3h See C7h See Section 9.1 CBh See Section 9.1 Section 9.1 CFh See ST10F271B/ST10F271E Reset value 0000h - - 00h 0000h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h ...
Page 119
... ST10F271B/ST10F271E Table 52. List of special function registers (continued) Physical Name address XPERCON b F024h E ZEROS b FF1Ch Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset Value depends on different triggered reset event. 3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals ...
Page 120
... EE20h CAN2: IF1 data A 2 EE22h CAN2: IF1 data B 1 EE24h CAN2: IF1 data B 2 EE14h CAN2: IF1 mask 1 EE16h CAN2: IF1 mask 2 EE1Ch CAN2: IF1 message control ST10F271B/ST10F271E Reset value 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h ...
Page 121
... ST10F271B/ST10F271E Table 53. List of XBus registers (continued) Name CAN2IF2A1 CAN2IF2A2 CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH RTCAL RTCCON RTCDH ...
Page 122
... XPWM module period register 1 EC24h XPWM module period register 2 EC26h XPWM module period register 3 EC10h XPWM module up/down counter 0 EC12h XPWM module up/down counter 1 EC14h XPWM module up/down counter 2 ST10F271B/ST10F271E Reset value XXXXh XXXXh XXXXh XXXXh XXXXh - - 00h XXXXh XXXXh XXXXh ...
Page 123
... ST10F271B/ST10F271E Table 53. List of XBus registers (continued) Name XPT3 XPW0 XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB Physical Description address EC16h XPWM module up/down counter 3 ...
Page 124
... Flash error register Flash non volatile access protection reg.0 Flash non volatile access protection reg.1 - high Flash non volatile access protection reg.1 - low Flash non volatile protection I register XBus Flash volatile temporary access unprotection register 0 ST10F271B/ST10F271E Description Reset value 0000h 0000h 0000h 0000h ...
Page 125
... ST10F271B/ST10F271E IDMANUF (F07Eh / 3Fh Table 55. IDMANUF Bit Manufacturer identifier MANUF 020h: STMicroelectronics manufacturer (JTAG worldwide normalization). IDCHIP (F07Ch / 3Eh Table 56. IDCHIP Bit Device identifier IDCHIP 110h: ST10F271 identifier (272). Device revision identifier REVID Xh: According to revision number. IDMEM (F07Ah / 3Dh) ...
Page 126
... PROGVPP R voltage DD voltage when programming EPROM or FLASH devices is calculated using the = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F271 (5V). DD voltage (no need of external V PP 0403h 110xh (x = silicon revision) F040h 0040h ST10F271B/ST10F271E Reset Value: 0040h PROGVDD R Function ) - 00h ...
Page 127
... ST10F271B/ST10F271E 24 Electrical characteristics 24.1 Absolute maximum ratings Table 59. Absolute maximum ratings Symbol V Voltage on V pins with respect to ground ( Voltage on V pin with respect to ground (V STBY STBY V Voltage on V pins with respect to ground (V AREF AREF V Voltage on V pins with respect to ground (V ...
Page 128
... INT I/O and V , expressed in Watt. This is the Chip Internal Power < P I/O INT and ( Using this value of K, the values ST10F271B/ST10F271E Value Min Max 4.5 5.5 4.5 5.5 -40 +125 -40 +150 Section 24 and may be neglected. On the other hand, ( neglected) is given by: ...
Page 129
... ST10F271B/ST10F271E Table 61. Thermal characteristics Symbol Thermal Resistance Junction-Ambient PQFP 144 - 3 0.65 mm pitch Θ TQFP 144 - 0.5 mm pitch JA TQFP 144 - 0.5 mm pitch on four layer FR4 board (2 layers signals / 2 layers power) Based on thermal characteristics of the package and with reference to the power consumption figures provided in next tables and diagrams, the following product classification can be proposed ...
Page 130
... HYSS V CC 750 HYS1 HYS2 V CC 400 HYS3 V CC 500 HYS4 V CC – – OL1 V CC – OL2 ST10F271B/ST10F271E Unit Test Condition max. 0.8 V – 0 – – Direct Drive mode DD 0.8 V – 0.3 V – 0.3 V – ...
Page 131
... ST10F271B/ST10F271E Table 63. DC characteristics (continued) Parameter Output high voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTOUT) (2) Output high voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output high voltage RPD Input leakage current (P5[15:0]) Input leakage current (all except P5[15:0], P2[0], RPD, P3[12], P3[15]) (4) Input leakage current (P2[0]) Input leakage current (RPD) Input leakage current ( P3[12], P3[15]) Overload current (all except P2[0]) ...
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... V). The absolute sum of input overload currents on all port pins may OV CPU and at maximum CPU clock frequency with all outputs DDmax RSTIN pin this implies I/O current is not considered. The device is IH IH1min ST10F271B/ST10F271E Unit Test Condition max. µA 200 T 400 µA T ...
Page 133
... ST10F271B/ST10F271E 10. The power supply current is a function of the operating frequency (f Figure 38 illustrated in the below. This parameter is tested at V disconnected and all inputs doing the following: - Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM - Watchdog Timer is enabled and regularly serviced - RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles - Four channel of XPWM are running (waves period ...
Page 134
... Electrical characteristics Figure 38. Supply current versus the operating frequency (RUN and IDLE modes) 150 100 134/180 [MHz] CPU ST10F271B/ST10F271E CC1 CC2 ...
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... ST10F271B/ST10F271E 24.6 Flash characteristics = 5 V ± 10 Table 64. Flash characteristics Parameter (2) Word Program (32-bit) (2)) Double Word Program (64-bit) Bank 0 Program (256K) (Double Word Program) Sector Erase (8K) Sector Erase (32K) Sector Erase (64K) (3) Bank 0 Erase (256K) Recovery from Power-Down (t PD (4) Program Suspend Latency ...
Page 136
... DNL CC –1 INL CC –1.5 OFS CC –1.5 –2.0 TUE CC –5.0 –7 – – – – S ST10F271B/ST10F271E 64Kbyte (EEPROM emulation) > 20 years > 20 years 10 years 1 year ≤ AREF DD Unit Test Condition max 0 AREF 5 mA Running mode µ ...
Page 137
... ST10F271B/ST10F271E Table 66. A/D converter characteristics Parameter 3) 8) Analog Switch Resistance 1. V can be tied to ground when A/D Converter is not in use: an extra consumption (around 200 AREF main V is added due to internal analogue circuitry not completely turned off: so suggested to DD maintain the V AREF setting bit ADOFF in ADCON register. ...
Page 138
... TCL * 560 TCL * 480 TCL * 960 TCL * 560 TCL * 1120 TCL * 800 TCL * 1120 TCL * 1600 TCL * 1120 ) and converts it into 10-bit digital data. The AREF ST10F271B/ST10F271E = 1/2TCL. A complete CPU Extra Total conversion TCL * 28 TCL * 388 TCL * 16 TCL * 436 TCL * 52 TCL * 532 ...
Page 139
... ST10F271B/ST10F271E These four error quantities are explained below using characteristic . Offset error Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage OFS). Gain error Gain error is the deviation between the actual and ideal A/D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF, once offset error is subtracted ...
Page 140
... AREF and V pins represents also the power supply of the analog AREF AGND could introduce error under certain conditions: for this AREF ST10F271B/ST10F271E Offset Error OFS Gain Error GE Bisector Characteristic (1) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential Non-Linearity Error (DNL) ...
Page 141
... ST10F271B/ST10F271E besides, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) ...
Page 142
... (that is typically bigger than the on-chip F : again considering the worst case in which C L (since the time constant in reality would be faster), the P1 τ 2 < ⋅ ST10F271B/ST10F271E (refer to the A ∆V < 0.5 LSB τ < << τ ...
Page 143
... ST10F271B/ST10F271E R sizing is obtained course, R combination with R definitively bigger than C charge transfer transient) will be much higher than V respected (charge balance assuming now The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to provide the extra charge to compensate the voltage drop on ...
Page 144
... Maximum Analog Source Voltage (V ● Analog Source Impedance (R ● Channel Switch Resistance (R ● Sampling Switch Resistance (R 144/180 is maximum, that is for instance 5V), A value: > 2048 10kHz 0 ): 25kHz C ): 1µ 5pF P1 ): 1pF P2 ): 4pF S ): 3mA INJ :12V AM) ): 100Ω 500Ω 200Ω AD ST10F271B/ST10F271E ⋅ ...
Page 145
... ST10F271B/ST10F271E 1. Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 2. Using the relation between possible to define consequence of step 1 and 2, RC can be chosen: 4. Considering the current injection limitation and supposing that the source can ...
Page 146
... The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). 146/180 2.0V Test Points 0.8V min. for a logic ‘1’ and 0.1V Timing Reference - 0.1V Points V OL Figure 45 ST10F271B/ST10F271E 2.0V 0.8V max for a logic ‘0’ 0. 0.1V OL changes of ±100mV. LOAD /V level occurs ( CPU refers to a PLL factor of 4 ...
Page 147
... ST10F271B/ST10F271E Figure 45. Generation mechanisms for the CPU clock Phase locked loop operation f XTAL f CPU Direct Clock Drive f XTAL f CPU Prescaler Operation f XTAL f CPU 24.8.3 Clock generation modes Table 68 Next associates the combinations of these three bits with the respective clock generation mode. Table 68. ...
Page 148
... XTAL instead of TCL XTAL max min ST10F271B/ST10F271E and the high and low time XTAL so the high and XTAL xlDC min is compensated, XTAL and t ) use the maximum duration ...
Page 149
... ST10F271B/ST10F271E an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin ...
Page 150
... Noise in the PLL loop. 150/180 PLL Input Prescaler Multiply by Divide XTAL – PLL bypassed XTAL is maximum time period of the PLL output clock and T ST10F271B/ST10F271E Output CPU Frequency Prescaler CPU 2 – F XTAL PLL XTAL 2 – F XTAL ...
Page 151
... ST10F271B/ST10F271E Jitter in the input clock PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter (frequency > PLL bandwidth) is attenuated @20dB/decade. ...
Page 152
... RSTIN pin low for just 1024 TCL (definitively not sufficient to get the PLL locked starting from free-running mode). 152/180 16MHz 24MHz 32MHz 40MHz 200 400 600 800 N (CPU clock periods) ). This feature allows to recover from a free ST10F271B/ST10F271E 64MHz 1000 1200 1400 ...
Page 153
... ST10F271B/ST10F271E Table 70. PLL characteristics (V Symbol T PLL Start-up time PSUP T PLL Lock-in time LOCK Single Period Jitter T JIT (cycle to cycle = 2 TCL) F PLL free running frequency free 1. Not 100% tested, guaranteed by design characterization. 24.8.11 Main oscillator specifications ± 10 Table 71. Main oscillator characteristics ...
Page 154
... SS A Parameter Conditions Start-up 1) Normal run 2) Peak to Peak 2) Sine wave middle 2) Stable V DD ST10F271 crystal C A ST10F271B/ST10F271E C = 35pF A max. min. typ. 430 Ω 850 Ω – 120 Ω 250 Ω – ) and the package capacitance 0 Value min. typ. max. ...
Page 155
... ST10F271B/ST10F271E Table 74. Minimum values of negative resistance (module) for 32kHz oscillator C = 6pF A 32kHz - The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C between XTAL3 and XTAL4 pins is globally assumed equal to 4pF. The external resistance between XTAL3 and XTAL4 is not necessary, since already present on the silicon ...
Page 156
... Note: All External Memory Bus Timings and SSC Timings reported in the following tables are granted by Design Characterization and not fully tested in production. 156/180 t3 t1 VIH2 t2 Symbol ST10F271B/ST10F271E t4 VIL2 t OSC Values TCL x [ALECTL] 2TCL x (15 - [MCTC]) 2TCL [MTTC]) ...
Page 157
... ST10F271B/ST10F271E 24.8.16 Multiplexed bus ± 10 ALE cycle time = 6 TCL + 2t Table 77. Multiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE Address hold after ALE 7 ALE falling edge to RD (with RW-delay) ALE falling edge to RD, WR ...
Page 158
... – 2TCL – – – 16 – 2TCL – – 2TCL – ST10F271B/ST10F271E Variable CPU Clock max. 3TCL – – – – – – 1.5 ns – ...
Page 159
... ST10F271B/ST10F271E Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE ALE t 6 CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH Address Address ...
Page 160
... Address/Data Bus (P0) WR WRL WRH 160/180 Address t 7 Address Address ST10F271B/ST10F271E Data Data out ...
Page 161
... ST10F271B/ST10F271E Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx Address Address ...
Page 162
... Read cycle t 6 Address/Data Bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx 162/180 Address t 7 Address Address ST10F271B/ST10F271E Data Data out ...
Page 163
... ST10F271B/ST10F271E 24.8.17 Demultiplexed bus ± 10 ALE cycle time = 4 TCL + 2t Table 78. Demultiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE 6 Address/Unlatched CS setup RD (with RW-delay) Address/Unlatched CS setup RD (no RW-delay) RD, WR low time t CC ...
Page 164
... – – – 16 – – 8 – – F refer to the next following bus cycle. ST10F271B/ST10F271E Variable CPU Clock 1/2 TCL = 1 to 64MHz min. max. – 4 – – 3TCL – – TCL – 10 – F 2TCL – – ...
Page 165
... ST10F271B/ST10F271E Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH Address ...
Page 166
... Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 166/180 Address ST10F271B/ST10F271E Data Data out ...
Page 167
... ST10F271B/ST10F271E Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx Address Data out ...
Page 168
... A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 168/180 Address ST10F271B/ST10F271E Data Data out ...
Page 169
... ST10F271B/ST10F271E 24.8.18 CLKOUT and READY ± 10 Table 79. CLKOUT and READY timings Symbol Parameter t CC CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 33 CLKOUT rising edge ALE falling edge ...
Page 170
... The next external bus cycle may start here. 170/180 READY Running cycle 1) wait state ST10F271B/ST10F271E MUX / Tri-state order to be safely synchronized. This is ...
Page 171
... ST10F271B/ST10F271E 24.8.19 External bus arbitration = 5V ± 10 Table 80. External bus arbitration timings Symbol HOLD input setup time CLKOUT CLKOUT to HLDA high BREQ low delay CLKOUT to HLDA low BREQ high delay t CC CSx release CSx drive ...
Page 172
... This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F271 requesting the bus. 2. The next ST10F271 driven bus cycle may start here. 172/180 ST10F271B/ST10F271E t 65 ...
Page 173
... ST10F271B/ST10F271E 24.8.20 High-speed synchronous serial interface (SSC) timing Master mode ±10 Table 81. SSC master mode timings Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time 301 t CC SSC clock low time 302 t CC SSC clock rise time ...
Page 174
... T = -40 to +125° Max. Baudrate 6.6 MBd @F = 40MHz CPU (<SSCBR> = 0002h) min. (2) 150 63 63 – – – ST10F271B/ST10F271E 305 306 Last out bit t t 307 308 Last in bit = 50pF L Variable Baudrate (1) ) (<SSCBR> = 0001h - FFFFh) max. min. max. ...
Page 175
... ST10F271B/ST10F271E Table 82. SSC slave mode timings Symbol Parameter Read data setup time before latch SR edge, phase error detection off t 317 (SSCPEN = 0) Read data hold time after latch SR edge, phase error detection off t 318 (SSCPEN = 0) 1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with 48MHz CPU clock and < ...
Page 176
... PQFP144 ST10F271B/ST10F271E OUTLINE AND MECHANICAL DATA PQFP144 0.10mm .004 Seating Plane C K ...
Page 177
... ST10F271B/ST10F271E Figure 64. TQFP144 mechanical data and package dimension DIM. MIN 0.05 A2 1.35 B 0. Note 1: Exact shape of each corner is optional. mm inch TYP. MAX. MIN. TYP. MAX. 1.60 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.007 0.009 0.011 0.20 0.003 0.008 22.00 0.866 20 ...
Page 178
... Tray PQFP144 Tape and reel Tray TQFP144 Tape and reel TQFP144 Tape and reel PQFP144 Tray Tray TQFP144 Tape and reel Tray TQFP144 Tape and reel ST10F271B/ST10F271E B/E Temperature CPU frequency range (°C) range (MHz) ° E -40 to +125 C ° B -40 to +125 C ° B ...
Page 179
... ST10F271B/ST10F271E 27 Revision history Table 84. Document revision history Date 12-Jul-2006 Revision 1 Initial release. Revision history Changes 179/180 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 180/180 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST10F271B/ST10F271E ...