ST10F271E STMICROELECTRONICS [STMicroelectronics], ST10F271E Datasheet - Page 171

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ST10F271E

Manufacturer Part Number
ST10F271E
Description
16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
ST10F271B/ST10F271E
24.8.19
External bus arbitration
V
Table 80.
1. Partially tested, guaranteed by design characterization.
Figure 59. External bus arbitration (releasing the bus)
1. The ST10F271 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
t
t
t
t
t
t
t
61
62
63
64
65
66
67
DD
Symbol
= 5V ± 10%, V
SR
CC
CC
CC
CC
CC
CC
CLKOUT
HOLD
HLDA
BREQ
CSx
(P6.x)
Others
External bus arbitration timings
HOLD input setup time
to CLKOUT
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
CSx release
CSx drive
Other signals release
Other signals drive
SS
Parameter
= 0V, T
t
1)
61
A
= -40 to +125°C, C
1)
1)
1)
min.
18.5
– 4
– 4
F
TCL = 12.5 ns
CPU
64
.
= 40 MHz
L
t
66
= 50pF
t
63
max.
12.5
12.5
20
15
20
15
t
t
62
64
3)
2)
1/2 TCL = 1 to 64MHz
Variable CPU Clock
min.
18.5
Electrical characteristics
– 4
– 4
max.
12.5
12.5
20
15
20
15
171/180
ns
ns
ns
ns
ns
ns
ns

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