ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 24

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263B
POWER SAVING MODES (Cont’d)
8.3 SLOW Mode
In Slow mode, the oscillator frequency can be di-
vided by 2 as selected by the SMS bit in the Mis-
cellaneous Register. The CPU and peripherals are
clocked at this lower frequency. Slow mode is
used to reduce power consumption, and enables
the user to adapt the clock frequency to the avail-
able supply voltage.
8.4 WAIT Mode
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0 to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to
24/132
Figure
18.
Figure 18. WAIT Mode Flow Chart
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
N
INTERRUPT
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
N
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
WFI INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
IF RESET
RESET
Y
ON
ON
OFF
CLEARED
ON
ON
ON
SET