ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 65

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
SCP1
DR7
7
7
PR Prescaling factor
SCP0
DR6
Figure
Figure
SCT2
1
3
DR5
35).
35).
SCT1
DR4
SCT0
DR3
SCP1
SCR2
DR2
0
0
SCR1 SCR0
DR1
SCP0
0
1
DR0
0
0
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock.
RR dividing factor
TR dividing factor
PR Prescaling factor
128
128
16
32
64
16
32
64
1
2
4
8
1
2
4
8
13
4
SCR2
SCT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SCP1
1
1
SCR1
SCT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ST7263B
SCP0
SCR0
SCT0
65/132
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1