ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 68

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263B
USB INTERFACE (Cont’d)
11.4.4 Register Description
DMA ADDRESS REGISTER (DMAR)
Read / Write
Reset Value: Undefined
Bits 7:0=DA[15:8] DMA address bits 15-8.
Software must write the start address of the DMA
memory area whose most significant bits are given
by DA15-DA6. The remaining 6 address bits are
set by hardware. See the description of the IDR
register and
Figure 38. DMA Buffers
68/132
DA15
7
DA14
Figure
DA13
DA15-6,000000
38.
DA12
DA11
DA10
DA9
DA8
0
101111
101000
100111
100000
011111
011000
010111
010000
001111
001000
000111
000000
INTERRUPT/DMA REGISTER (IDR)
Read / Write
Reset Value: xxxx 0000 (x0h)
Bits 7:6 = DA[7:6] DMA address bits 7-6.
Software must reset these bits. See the descrip-
tion of the DMAR register and
Bits 5:4 = EP[1:0] Endpoint number (read-only).
These bits identify the endpoint which required at-
tention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.
Bits 3:0 = CNT[3:0] Byte count (read only).
This field shows how many data bytes have been
received during the last data reception.
Note: Not valid for data transmission.
DA7
7
DA6
Endpoint 2 RX
Endpoint 1 RX
Endpoint 0 RX
Endpoint 2 TX
Endpoint 1 TX
Endpoint 0 TX
EP1
EP0
CNT3
Figure
CNT2
38.
CNT1
CNT0
0