k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 19

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
BOUNDARY SCAN EXIT ORDER
*Note :
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode.
3. Two RFU balls(#56and #57) and one RFM ball(#20) in the scan order will be read as a logic”0".
SCAN PIN DESCRIPTION
*Note :
1. When SEN is asserted, no commands are to be executed by the GDDR3 SDRAM. This applies to both user commands and manufacturing commands which may exist
2. All scan functionalities are valid only after the appropriate power-up and initialization sequence. (RES and CKE, to set the ODT of the C/A)
3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ’s will be disabled. It is not necessary for the termination
4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE’s should be provided to top and bottom devices to access the scanned
while RES is de-asserted.
to be calibrated.
output. When either of the devices is in scan mode, SOE for the other device which not in a scan will be disabled.
BIT#
Package Ball
10
12
11
1
2
3
4
5
6
7
8
9
D-2
V-9
F-9
V-4
A-9
BALL
B-10
C-10
C-11
D-10
B-11
D-11
D-3
C-2
C-3
B-2
B-3
A-4
Symbol
SOUT
BIT#
SOE
SSH
SCK
SEN
22
23
24
13
14
15
16
17
18
19
20
21
Function
BALL
WDQS0
Normal
E-10
G-10
H-10
F-10
E-11
F-11
H-11
J-11
J-10
G-9
H-9
L-9
RES
RFU
CS
MF
BIT#
Output
34
35
25
26
27
28
29
30
31
32
33
36
Type
Input
Input
Input
Input
BALL
Scan shift.
Capture the data input from the pad at logic LOW and shift the data on the
chain at logic HIGH.
Scan Clock. Not a true clock, could be a single pulse or series of pulses.
All scan inputs will be referenced to rising edge of the scan clock.
Scan Output.
Scan Enable.
Logic HIGH would enable the device into scan mode and will be disabled at
logic LOW. Must be tied to GND when not in use.
Scan Output Enable.
Enables (registered LOW) and disables (registered HIGH) SOUT data.
This pin will be tied to VDD or GND through a resistor (typically 1K Ω ) for
normal operation. Tester needs to overdrive this pin guarantee the required
input logic level in scan mode.
M-10
K-10
M-11
N-11
N-10
P-10
R-11
K-11
L-10
P-11
M-9
K-9
19 / 54
BIT#
37
39
40
43
45
46
47
48
38
41
42
44
BALL
R-10
T-10
T-11
M-3
R-3
R-2
N-3
N-2
P-3
P-2
T-3
T-2
Description
BIT#
256M GDDR3 SDRAM
59
49
50
51
52
53
54
55
56
57
58
60
BALL
Rev. 1.3 May 2007
M-2
M-4
H-2
H-3
H-4
L-3
K-4
K-3
K-2
L-4
J-3
J-2
BIT#
61
63
64
66
67
62
65
BALL
G-4
G-3
F-4
F-2
E-2
F-3
E-3