k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 36

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
Random WRITE Cycles
COMMAND
ADDRESS
WDQS
/CK
NOTE
DM
CK
DQ
:
WRITE
1. DI b, etc. = data-in for column b, etc.
2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order.
3. Programmed burst length = 4 cases shown.
4. Each WRITE command may be to any bank.
5. Last write command will have the rest of the nibble on T8 and T8n
6. Write latency is set to 3
Bank
Col b
T0
t
DQSS
(NOM)
NOP
T1
WRITE
Bank
Col x
T2
36 / 54
NOP
DI
T3
b
T3n
DI
DON’T CARE
b
WRITE
Bank
Col g
T4
DI
b
T4n
DI
b
256M GDDR3 SDRAM
NOP
T5
TRANSITIONING DATA
DI
x
T5n
DI
Rev. 1.3 May 2007
x
NOP
T6
DI
x
T6n
DI
x
NOP
T7
DI
g
DI
g