k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 8

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

A0-A7, A9-A11
K4J55323QI
COMMAND
7.2 INITIALIZATION
those
BA0, BA1
GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
WDQS
RDQS
1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)
2. Required minimum 100us for the stable power before RESET pin transition to HIGH
3. Minimum 200us delay required prior to applying any executable command after stable power and clock.
4. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be
5. Issue a PRECHARGE ALL command following after NOP command.
6. Issue a EMRS command (BA1BA0="01") to enable the DLL.
7. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
8. Issue a PRECHARGE ALL command
9. Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
Following these requirements, the GDDR3 SDRAM is ready for normal operation.
V
V
RES
CKE
CKE
DDQ
V
REF
DM
CK
CK
DQ
DD
A8
- The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
brought to HIGH,
20K clock cycles are required between the DLL to lock.
voltage ramps are without any slope reversal
be in a High-Z state, all active terminators off, and all DLLs off.
specified may result in undefined operation.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
T=10ns
Power-up:
V
CK stable
t
ATS
DD
and
t
ATH
T = 200us
t
t
IS
IS
NOP
T0
t
t
IH
IH
High
High
High
t
CH
t
CL
ALL BANKS
Precharge
All Banks
t
IS
PRE
T1
t
IH
8 / 54
tRP
Load Extended
Mode Register
t
t
t
IS
IS
IS
CODE
BAO=H,
BA1 =L
CODE
Ta0
LMR
t
t
t
IH
IH
IH
tMRD
Load Mode
REF
DLL Reset
Register
CODE
BAO=L,
BA1 =L
CODE
Tb0
LMR
is applied )
tMRD
ALL BANKS
Precharge
All Banks
t
IS
Tc0
PRE
256M GDDR3 SDRAM
t
IH
tRP
20K
Auto Refresh
Td0
1st
AR
Rev. 1.3 May 2007
tRFC
Auto Refresh
Te0
AR
2nd
tRFC
ACT
Tf0
RA
RA
BA