k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 3

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
1.0 FEATURES
2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
• 1.8V + 0.1V power supply for device operation for -BC**
• 1.8V + 0.1V power supply for I/O interface for -BC**
• 1.9V + 0.1V power supply for device operation for -BJ**
• 1.9V + 0.1V power supply for I/O interface for -BJ**
• On-Die Termination (ODT)
• Output Driver Strength adjustment by EMRS
• Calibrated output drive
• 1.8V Pseudo Open drain compatible inputs/outputs
• 4 internal banks for concurrent operation
• Differential clock inputs (CK and CK)
• Commands entered on each positive CK edge
• CAS latency : 7, 8, 9, 10, 11, 12 (clock)
• Programmable Burst length : 4 and 8
• Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
2.0 ORDERING INFORMATION
3.0 GENERAL DESCRIPTION
ricated with SAMSUNG
mance up to 8.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
The K4J55323QI is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fab-
K4J55323QI-BC12
K4J55323QI-BC14
K4J55323QI-BJ1A
K4J55323QI-BJ11
Part NO.
’s
high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
Max Freq.
1000MHz
900MHz
800MHz
700MHz
3 / 54
Max Data Rate
• RDQS edge-aligned with data for READs
• WDQS center-aligned with data for WRITEs
• Data Mask(DM) for masking WRITE data
• Auto & Self refresh modes
• Auto Precharge option
• 32ms, auto refresh (4K cycle)
• 136 Ball FBGA
• Maximum clock frequency up to 1000MHz
• Maximum data rate up to 2.0Gbps/pin
• DLL for outputs
• Boundary scan function with SEN pin
• Mirror function with MF pin
2.0Gbps/pin
1.8Gbps/pin
1.6Gbps/pin
1.4Gbps/pin
VDD&VDDQ
1.9V+0.1V
1.8V+0.1V
256M GDDR3 SDRAM
Rev. 1.3 May 2007
136 Ball FBGA
Package