k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 32

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
7.9.3 WRITEs
column and bank addresses are provided with the WRITE command, and auto pre-
charge is either enabled or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
edge of WDQS following the WRITE latency set in the mode register and subsequent
data elements will be registered on successive edges of WDQS. Prior to the first valid
WDQS edge a half cycle is needed and specified as the WRITE Preamble; the half
cycle in WDQS following the last data-in element is known as the write postamble.
(t
show the nominal case, and where the two extreme cases (i.e., t
t
shows the nominal case and the extremes of tDQSS for a burst of 4. Upon comple-
tion of a burst, assuming no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored. Data for any WRITE
burst may not be truncated with a subsequent WRITE command. The new WRITE
command can be issued on any positive edge of clock following the previous WRITE
command after the burst has completed. The new WRITE command should be
issued x cycles after the first WRITE command should be equals the number of
desired nibbles (nibbles are required by 4n-prefetch architecture).
READ figure. Full-speed random write accesses within a page or pages can be per-
formed as shown in Random WRITE cycles figure. Data for any WRITE burst may be
followed by a subsequent READ command.
mand. To follow a WRITE the WRITE burst, t
PRECHARGE figure.
mand.
WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting
Data for any WRITE burst can not be truncated by a subsequent PRECHARGE com-
During WRITE bursts, the first valid data-in element will be registered in a rising
The time between the WRITE command and the first valid falling edge of WDQS
DQSS(max)
An example of nonconsecutive WRITEs is shown in Nonconsecutive WRITE to
Data for any WRITE burst may be followed by a subsequent PRECHARGE com-
DQSS
) is specified with a relative to the write latency. All of the WRITE diagrams
) might not be intuitive, they have also been included. Write Burst figure
WR
should be met as shown in WRITE to
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DQSS(min)
and
A0-A7, A9
BA0, BA1
A10, A11
256M GDDR3 SDRAM
/RAS
/CAS
CKE
/WE
/CK
/CS
CK
A8
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
WRITE Command
Rev. 1.3 May 2007
HIGH
DIS AP
EN AP
CA
BA
DON’T CARE