k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 39

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
7.9.4 PRECHARGE
bank or the open row in all banks. The bank(s) will be available for a subsequent
row access some specified time (t
issued. Input A8 determines whether one or all banks are to be precharged, and
in the case where only one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0, BA1 are treated as
"Don’t Care." Once a bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being issued to the bank.
7.9.5 POWER-DOWN (CKE NOT ACTIVE)
times an access is in progress; from the issuing of a READ or WRITE command
until completion of the burst. For READs, a burst completion is defined when the
Read Postamble is satisfied; For WRITEs, a burst completion is defined BL/2
cycles after the Write Postamble is satisfied.
when there is a row active in any bank, this mode is referred to as active power-
down. Entering power-down deactivates the input and output buffers, excluding
CK,/CK and CKE. For maximum power savings, the user has the option of dis-
abling the DLL prior to entering power-down. However, power-down duration is
limited by the refresh requirements of the device, so in most applications,the self-
refresh mode is preferred over the DLL-disabled power-down mode.
the inputs of the GDDR3 SDRAM, while all other input signals are "Don’t Care"
except data terminator disable command.
conjunction with a NOP or DESELECT command). A valid executable command
may be applied tPDEX later.
The PRECHARGE command is used to deactivate the open row in a particular
When in power-down, CKE LOW and a stable clock signal must be maintained at
The power-down state is synchronously exited when CKE is registered HIGH (in
Unlike SDR SDRAMs,GDDR3(x32) SDRAM requires CKE to be active at all
Power-down is entered when CKE is registered LOW. If power-down occurs
Power-Down
COMMAND
* Once the device enters the power down mode, it should be in NOP state at least for 10ns
CKE
/CK
CK
No PEAD/WRITE
access in progress
VALID
T0
RP
) after the PRECHARGE command is
t
IS
NOP
T1
* Enter power - down mode
T2
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Ta0
A0-A7, A9-A11
t
IS
NOP
Ta1
BA0, BA1
Exit power - down mode
256M GDDR3 SDRAM
PRECHARGE Command
(if A8 is LOW; otherwise "Don’t Care")
/RAS
/CAS
CKE
/WE
/CK
/CS
CK
A8
Rev. 1.3 May 2007
BA=Bank Address
NOP
Ta2
t
HIGH
PDEX
ALL BANKS
ONE BANK
DON’T CARE
BA
VALID
Ta7