ch7006c Chrontel, ch7006c Datasheet - Page 10

• Manufacturer Part Number: ch7006c
• Description: Ch7006 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
4.3 Functional Description
The CH7006 is a TV-output companion chip to graphics controllers providing digital output in either YUV or RGB
format. This solution involves both hardware and software elements which work together to produce an optimum
TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are
integrated onchip. Onchip circuitry includes memory, memory control, scaling, PLL, DAC, filters, and NTSC/PAL
encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to
ensure that the high-quality video signals are not affected by drift issues associated with analog components. No
additional adjustment is required during manufacturing.
CH7006 is ideal for PC motherboards, web browsers, or VGA add-in boards where a minimum of discrete support
components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.
4.3.1 Architectural Overview
The CH7006 is a complete TV output subsystem which uses both hardware and software elements to produce an
image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a
compatible TV output from a VGA input involves a relatively straightforward process. This process includes a
standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame
sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum
computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and
filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with
minimal artifacts from the conversion process.
As a key part of the overall system solution, the CH7006 software establishes the correct framework for the VGA
input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600),
the CH7006 software may be invoked to establish the appropriate TV output display. The software then programs
the various timing parameters of the VGA controller to create an output signal that will be compatible with the
chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates,
total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7006 can render
a superior TV image without the added cost of a full frame buffer memory – normally used to implement features
such as scaling and full synchronization.
The CH7005 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel
clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory.
The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line and 5-
line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to
either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling
reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through
digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to
composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.
10
Table 10. RGB 8-bit Multiplexed Mode (24-bit Color)
Pixel#
Bus Data
Format
IDF#
MUST BE used for each DAC connecting to TV (Refer to AN-38 for details).
In order to minimize the hazard of ESD, a set of protection diodes
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P0b
G0[7]
G0[6]
G0[5]
G0[4]
G0[3]
G0[2]
G0[1]
G0[0]
P0c
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
P1a
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
RGB 8-bit
6
G1[7]
G1[6]
G1[5]
G1[4]
G1[3]
G1[2]
G1[1]
G1[0]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
P1c
201-0000-026 Rev. 2.8, 6/24/2004
B2[7]
B2[6]
B2[5]
B2[4]
B2[3]
B2[2]
B2[1]
B2[0]
P2a
P2b
G2[7]
G2[6]
G2[5]
G2[4]
G2[3]
G2[2]
G2[1]
G2[0]
CH7006C
P2c
R2(7)
R2(6)
R2(5)
R2(4)
R2(3)
R2(2)
R2(1)
R2(0)