ch7006c Chrontel, ch7006c Datasheet - Page 36

• Manufacturer Part Number: ch7006c
• Description: Ch7006 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Note: POUTP (bit 4) is used to invert the P-OUT signal.
Note: DSEN (bit4) controls the BCO / Data Start I/O pin. When this bit is low, the pin continues to operate as the BCO
pin described in the BCO register description. When this bit is high, the pin becomes an input for the Data Start signal.
PLL Control Register
The following PLL and memory controls are available through the PLL control register:
MEM5V
PLL5VA
PLL5VD
PLLS
PLLCAP
PLLCPI
36
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
7
7
7
MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the
memory supply is 3.3 volts.
PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is
used when the phase-locked loop analog supply is 3.3 volts.
PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when
the phase-locked loop digital supply is 3.3 volts (default).
PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL
supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL
supply) PLLS should be 0, and five stages are used.
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.
Mode is shown below
PLLCHI controls the charge pump current of the PLL. The default value should be used.
6
6
6
5
5
5
PLLCPI
R/W
0
4
P-OUTP
R/W
0
4
DSEN
R/W
1
4
PLLCAP
R/W
0
3
FSCI19
R/W
0
3
FSCI15
R/W
0
3
PLLS
R/W
1
2
FSCI18
0
2
FSCI14
0
2
PLL5VD
0
201-0000-026 Rev. 2.8, 6/24/2004
R/W
R/W
R/W
Symbol:
Address: 1BH
Bits: 8
Symbol:
Address: 1CH
Bits: 6
Symbol: PLLC
Address: 20H
Bits: 6
1
FSCI17
R/W
0
1
FSCI13
R/W
0
1
PLL5VA
R/W
1
CH7006C
0
FSCI16
R/W
0
0
FSCI12
R/W
0
0
MEM5V
R/W
0