ch7006c Chrontel, ch7006c Datasheet - Page 29

• Manufacturer Part Number: ch7006c
• Description: Ch7006 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Black Level Register
This register sets the black level. The luminance data is added to this black level, which must be set between 90 and
208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100
for NTSC-J.
Horizontal Position Register
The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to
achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0]
plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed
image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the
image position by 4 input pixels.
Vertical Position Register
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically cen-
tered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync)
used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses).
Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen.
Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one
TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is
the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number
should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When pan-
ning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next
step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a
number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
201-0000-026 Rev. 2.8, 6/24/2004
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
7
BL7
R/W
0
7
HP7
R/W
0
7
VP7
R/W
0
6
BL6
R/W
1
6
HP6
R/W
0
6
VP6
R/W
0
5
BL5
R/W
1
5
HP5
R/W
0
5
VP5
R/W
0
4
BL4
R/W
1
4
HP4
R/W
0
4
VP4
R/W
0
3
BL3
R/W
1
3
HP3
R/W
0
3
VP3
R/W
0
2
BL2
R/W
1
2
HP2
R/W
0
2
VP2
R/W
0
Symbol: BLR
Address: 09H
Bits: 8
Symbol: HPR
Address: 0AH
Bits: 8
Symbol: VPR
Address: 0BH
Bits: 8
1
BL1
R/W
1
1
HP1
R/W
0
1
VP1
R/W
0
CH7006C
0
BL0
R/W
1
0
HP0
R/W
0
0
VP0
R/W
0
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