ch7006c Chrontel, ch7006c Datasheet - Page 45

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ch7006c

Manufacturer Part Number
ch7006c
Description
Ch7006 Digital Pc To Tv Encoder
Manufacturer
Chrontel
Datasheet

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CHRONTEL
7.3 Clock - Master, Sync - Master Mode
201-0000-026 Rev. 2.8, 6/24/2004
DVDD2
V
V
t1
t2
t3
t4
t5
t6
t7
Symbol
P-OUT
H
V
XCLK
XCLK*
D[11:0]
DS
OH
OL
Digital I/O Supply Voltage
Output High level of interface signals
Output Low level of interface signals
P-OUT rise/fall time w/15pF load, VREF = 1.65 V
XCLK & XCLK* rise/fall time w/15pF load
Setup time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
Hold time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
D[11:0], H, V & DS rise/fall time w/15pF load
Hold time:
P-OUT to HSYNC, VSYNC delay
(P-OUT=VREF) to (XCLK =XCLK*) delay
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OH
OH
OH
OL
OL
OL
OL
OH
OH
OH
OL
OL
OL
Parameter
t6
t5
64 PIXELS
1 VGA
Line
t5
t2
DVDD2 - 0.2
t7
Min
-0.2
1.7
1.5
1.5
1
1
2
t1
P0a
Typ
1.5
5
5
5
t3
P0b
t3
t1
DVDD2 + 0.2
P1a
Max
3.6
0.2
2.5
CH7006C
7
P1b
9
t4
P2a
P2b
t5
Unit
ns
ns
ns
ns
ns
ns
ns
V
V
V
45

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