ch7006c Chrontel, ch7006c Datasheet - Page 3

• Manufacturer Part Number: ch7006c
• Description: Ch7006 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
3.2 Pin Descriptions
Table 1. Pin Descriptions
201-0000-026 Rev. 2.8, 6/24/2004
44Pin
LQFP
12,13,
14,15,
42,43,
10,11,
6,7,9,
1,2,
3,4,
44
37
39
41
40
35
32
33
24
22
In/Out
In/Out
In/Out
Type
Out
Out
In
In
In
In
In
Symbol
DS/BCO
D15-D0
XO/FIN
P-OUT
XCLK
RSET
Y/R
XI
V
H
Digital Pixel Inputs
These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or
16-bit non-multiplexed formats, determined by the input mode setting (see Registers
and Programming section). Inputs D0 - D7 are used when operating in 8-bit
multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs
D0 - D15 are used when operating in 16-bit mode. The data structure and timing
sequence for each mode is described in the section on Digital Input Port.
Pixel Clock Output
The CH7006, operating in master mode, provides a pixel data clocking signal to the
VGA controller. This clock will only be provided in master clock modes and will be tri-
stated otherwise. This pin provides the pixel clock output signal (adjustable as 1X,2X
or 3x) to the VGA controller (see the section on Digital Video Interface, Registers and
Programming for more details). The capacitive loading on this pin should be kept to a
minimum.
Pixel Clock Input
To operate in a pure master mode, the P-OUT signal should be connected to the
XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a
reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-
OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7006
accepts an external pixel clock input at this pin. The capacitive loading on this pin
should be kept to a minimum.
Vertical Sync Input/Output
This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical
sync to the VGA controller. The capacitive loading on this pin should kept to a
minimum.
Horizontal Sync Input/Output
This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal
sync to the VGA controller. The capacitive loading on this pin should be kept to a
minimum.
Data/Start (input) / Buffered Clock (output)
When configured as an input, the rising edge of this signal identifies the first active
pixel of data for each active line.
When configured as an output this pin provides a buffered clock output. The output
clock can be selected using the BCO register (17h) (see Registers and
Programming).
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between
XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should
be connected to ground.
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An
external CMOS compatible clock can be connected to XO/FIN as an alternative.
Reference Resistor
A 360 Ω resistor with short and wide traces should be attached between RSET and
ground. No other connections should be made to this pin.
Luminance Output
A 75 Ω termination resistor with short traces should be attached between Y and
ground for optimum performance. In normal operating modes other than SCART and
RGB bypass, this pin outputs the composite video signal. In SCART and RGB
Bypass modes, this pin outputs the red signal.
Description
CH7006C
3