ch7006c Chrontel, ch7006c Datasheet - Page 28

• Manufacturer Part Number: ch7006c
• Description: Ch7006 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
The Clock Mode Register also contains the following bits:
Start Active Video Register
This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start,
to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value
contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set
anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading
edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X
clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the
DS/BCO pin as a data start input, this register should be set to decimal value 11.
Position Overflow Register
This position overflow register contains the MSB values for the SAV, HP, and VP values, as follows:
28
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the
• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the
• CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the
• VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register”).
• HP8 (bit 1) is the MSB of the horizontal position value (see explanation under “Horizontal Position
• SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video
negative edge, one selects the positive edge.
14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as
a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced
to one.
subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the
subcarrier to free-run, and should be used when the ACIV bit is set to one.
Register”).
Register”).
7
SAV7
R/W
0
7
6
SAV6
R/W
0
6
5
SAV5
R/W
0
5
4
SAV4
R/W
0
4
3
SAV3
R/W
0
3
2
SAV2
R/W
0
2
SAV8
R/W
0
201-0000-026 Rev. 2.8, 6/24/2004
Address: 07H
Bits: 8
Address: 08H
Bits: 3
Symbol: SAV
Symbol: PO
1
SAV1
R/W
0
1
HP8
R/W
0
CH7006C
0
SAV0
R/W
0
0
VP8
R/W
0